United States

A novel Ferroelectric FET (FeFET) structure to enable multi-level cell (MLC) storage using a cleaved gate (CG) is proposed for the first time. The CG-FeFET’s gate is divided into two gates by an insulator. The CG-FeFET is optimized based on well-calibrated TCAD models. We perform an extensive design space exploration by evaluating: 1) the impact of the length of separation oxide (LOX) between source side gate (G_S) and drain side gate (G_D); 2) whether reading from G_S or G_D is better; 3) the best placement of the insulator between the two gates comparing symmetric (LG_S= LG_D) vs. asymmetric (LG_S≠LG_D) structure.  

IRPS 2022

Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

This paper presents a synthesized version of the silicon odometer aging sensor for measuring the frequency degradation caused by device degradation mechanisms in high volume semiconductor products. In the design, three ring oscillators (ROSCs) composed of inverter, NAND, and NOR gates are implemented in register-transfer-level (RTL), with the ability to be stressed in an AC or DC stress condition. The new odometer has product level features such as calibration-free operation, automatic frequency dead zone escape, and start-up glitch removal. The odometer verilog code was synthesized and automatically placed-and-routed in three different technologies using standard ASIC design tools. As a proof of concept, we show aging data collected from a 65nm test chip with 12 synthesized odometer instances.  

A Calibration - Free Synthesizable Odometer Featuring Automatic Frequency Dead Z one Escape and Start - up Glitch Removal

Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies

We applied Monte Carlo (MC) aging simulation flow to explain measured aging effects of PUF (Physically Unclonable Function) circuit. Simulation data provides a good understanding of how PUF circuit might fail with the NBTI effect. The flow predicts updated design shows better reliability result. We demonstrated that NBTI variation model requires correct consideration of the MOSFET device size. 

Reliability Analysis of Physically Unclonable Function by Using Aging Variability Simulation

We propose an aging degradation suppression scheme at constant performance by controlling supply voltage and body bias for an FDSOI device. Reducing supply voltage while increasing body bias can maintain performance and suppress dynamic power and aging degradation caused by BTI. From measurement results of ring oscillators in a 65 nm    FDSOI, NBTI- and PBTI-induced degradations can be reduced by 29% and 10% at 1.5 V supply voltage and 0.15 V forward body bias paying the penalty of 2x leak power increase.

An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process

In this work, we demonstrate that proper engineering of VTH in ferroelectric FET is necessary to ensure correct array operation for in-memory computing applications. We highlight that for all current-based computing operations, it is necessary to keep both the low-VTH and high-VTH states positive to cut off the leakage for grounded unselected cells. To reach that design target, we systematically evaluate various design options for VTH engineering, including the gate metal work function, the body bias, and the buried oxide thickness, using calibrated TCAD. We establish the design guidelines for VTH engineering to ensure the successful operation of in-memory computing.

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Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage

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A Calibration - Free Synthesizable Odometer Featuring Automatic Frequency Dead Z one Escape and Start - up Glitch Removal

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