United States

RF reliability of 40-nm PDSOI nFET power amplifier (PA) cell at 26.5GHz is investigated. DC and RF stresses are applied in conducting and non-conducting hot carrier stress mode to study the PA cell RF and DC degradation behaviour. The relationship between DC and large-signal RF performance under various RF stress conditions is investigated using DC and RF metrics. The degradation rate depends on RF power and terminal voltages, where ~8X lower degradation is observed at low VGS. During RF stress, the DC performance degradation rate is higher in the linear operating region than the saturation region. The impact of RF stress is amplified in the presence of DC stress, accelerating the degradation of PA cells. For different VGS under RF stress conditions, the lifetime of the PA cell is calculated and compared.

IRPS 2022

RF Reliability of CMOS-Based Power Amplifier Cell for 5G mmWave Applications

hot carrier degradation

mmwave

power amplifier

technical paper

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/6b7a695cee2a4e6d07c0594938f00e41.png)](https://drive.google.com/file/d/1_V_fHL72jJWTmq-pUe-JJAR97y3dN5RX/view?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/924447c4755e4e804db480b0504f6c13.png)](https://drive.google.com/drive/folders/1Mxu8R6jiCM_F1m_4pFdqgVKDfYaoTbtn?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)

 


![](https://assets.underline.io/uploads/markdown_image/1/image/e1ce7df3286ab3a750966a5bf555716e.png)
 


**PROGRAM AT A GLANCE:**
 

![](https://assets.underline.io/uploads/markdown_image/1/image/fd55e96d31b53ac223d4e9b8d0186848.png)

 

**2022 IEEE International Reliability Physics Symposium has gone mobile!**

![](https://assets.underline.io/uploads/markdown_image/1/image/07a1cc9ee775657110a89eddbcc41388.jpg)

 


![](https://assets.underline.io/uploads/markdown_image/1/image/7a5e45b43771adf5ae4d3f97c1861ac1.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/a0cab03a0ec30cc71c71b5efec2ba603.png)](https://www.amd.com/en)[![](https://assets.underline.io/uploads/markdown_image/1/image/2921931b8aa0a090d96fd463670a0305.png)](https://www.cisco.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/d0cd3844560c9bdf8d4303b36d82dc69.png)](https://amazon.jobs/en/teams/lab126/)

![](https://assets.underline.io/uploads/markdown_image/1/image/c849d66095021f867725ff54b2c1f53e.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/8e648631fe7093b9613454de264d6745.png)](https://www.intel.com/content/www/us/en/homepage.html)[![](https://assets.underline.io/uploads/markdown_image/1/image/76970c33d96c19445badc60c21d890e8.png)](https://www.kioxia.com/en-emea/top.html)[![](https://assets.underline.io/uploads/markdown_image/1/image/546ecacb92116a8373a0cb2b3462dc1e.png)](https://about.google/)[![](https://assets.underline.io/uploads/markdown_image/1/image/91dca9e7aff5399ce0ea709d196c4f6a.png)](https://www.ibm.com/hr-en)[![](https://assets.underline.io/uploads/markdown_image/1/image/d1a1c95a5b0b551edea10f686f959c0d.png)](https://www.qualcomm.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/fa628a3cef7a5300e4ab59da0e0552fa.png)](https://www.samsung.com/hr/smartphones/galaxy-s22-ultra/?page=home)[![](https://assets.underline.io/uploads/markdown_image/1/image/948a0108c6b1b84e336b6f39bbc57fcf.png)](https://www.micron.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/74e631e654862d71a16d009817467e5c.png)](https://www.nvidia.com/en-eu/geforce/)[![](https://assets.underline.io/uploads/markdown_image/1/image/224a109509478bb0c4d361401ba65fae.png)](https://www.tsmc.com/english)[![](https://assets.underline.io/uploads/markdown_image/1/image/d70304be54ef831492c3cb99d8c1f3c7.png)](https://www.tel.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/7e60586f1c46e0157f2f452d4005fb54.png)](https://gf.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/e1c9bbe8892bbd4d89b81de064f31dfa.png)](https://www.appliedmaterials.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/dc19add30e3105172bdc93580e944dee.png)](https://www.ti.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/8e81ebc466ddd94f3fde7f3cdebb86c0.png)](https://www.skhynix.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/ccfa43258b058874e38e5903f79e63bc.png)](https://www.st.com/content/st_com/en.html)

 
![](https://assets.underline.io/uploads/markdown_image/1/image/e4c5690a7016a468518eeab6ed0f7e56.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/c33da95f78e91c05d51b787f02a1af01.png)](https://www.infineon.com/)
![](https://assets.underline.io/uploads/markdown_image/1/image/e708450912afd1718c5af9e9dfd70d3f.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/ffd1b2531ec1531672693a786e5a1b37.png)](https://eds.ieee.org/)[![](https://assets.underline.io/uploads/markdown_image/1/image/0a58c969093f21f088af904b1cb4e112.png)](https://rs.ieee.org/)

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

We investigate the impact of charge-trapping on ferroelectric (FE) switching and its influence on memory window (MW) and retention of FeFET. Fabricated FinFETs with ferroelectric gate stack were used to study defects properties (within HZO), trapping/FE-switching interplay, and dynamics. Starting from the electronic-assisted nucleation of FE domains, we investigated the interface charging and degradation, as well as their impact on the polarization compensation, MW and stabilization of the retention. Finally, a balance between those competing processes was analyzed and a retention model of FeFET (capturing behavior over device’s lifetime) was developed 

Electron-assisted switching in FeFETs: MW dynamics – retention - trapping mechanisms and correlation

In SOT-MRAM, the writing path is decoupled from the reading path and therefore considered robust against MgO breakdown in the MTJ. At operation, high current densities flow through the thin metallic SOT layer underneath the MTJ. We find that the SOT track is robust against electromigration, but we observe failure of the MTJ. A thorough chemical analysis indicates the activation of diffusion mechanisms that degrade the free layer and MgO tunnel barrier.

MTJ degradation in SOT-MRAM by self-heating-induced diffusion

Ovonic Threshold Switching Selector faces challenges of VTH stability in intensive applications due to relaxation and the degradation upon endurance cycling. This work investigates the first fire (FF) voltage effects and mechanisms related to the switching characteristics on GeCTe-based selectors. Higher VTH stability and more uniform Ioff-VTH control during endurance cycling were achieved by higher FF design. A power-law model with strong correlation between endurance and pulse-energy was also demonstrated in this study.

Investigation of First Fire Effect on VTH Stability and Endurance in GeCTe Selector

Temperature dependence of charge capture and emission in HfO2 and ferroelectric doped HfO2 are examined over a wide temperature range. Sizeable threshold voltage (Vth) instabilities are observed under cryogenic conditions, contrary to expectation of Arrhenius-based defect freeze-out. The observed data is modelled with the ultra-fast defect levels, located close to the silicon channel. The impact of these traps at room temperature on ferroelectric devices is significant: capture and emission times lie in the range applied for device operation, and can explain the read-after-write delay incorporated in Si-based ferro (FE-)FET operation. 


Modelling ultra-fast threshold voltage instabilities in Hf-based ferroelectrics

Design of reliable and high-performance RF power amplifiers in CMOS technologies is becoming more challenging due to the increasing reliability issues as we approach the scaling limit. To provide insight on hot-carrier injection (HCI) degradation at RF frequencies, this paper presents a comprehensive analysis to study this effect on different PA architectures based on their mission profile with a quasi-static approach. Sensitivity analysis on power amplifier RF performance is also discussed to offer a better understanding on the importance of accurate device and aging behavior modeling. 

Comprehensive Analysis of RF Hot-Carrier Reliability Sensitivity and Design Explorations for 28GHz Power Amplifier Applications

Power device characteristics are affected by X-rays used during the inspection of power modules. In this study, the effects of materials and structures of power MOSFETs on the overall degradation were analyzed by irradiating Si MOSFETs and SiC MOSFETs with X-rays using a commercial inspection system. In addition, the effectiveness of thermal and gate voltage annealing was investigated for the irradiated devices. The experimental results confirmed the high radiation tolerance of SiC MOSFETs. In addition, the irradiated devices exhibited difficulty in recovering the shifted threshold voltage without compromising the reliability of the device, indicating that the effects of degradation persisted for a long time.

Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Its Recovery

Forty nine silicon carbide 150 mm wafers from three commercial vendors to be used for fabricating MOSFETs were examined by UVPL imaging to count their concentration of basal plane dislocations, inclusions, micropipes and trapezoids. The wafers were from three vendors, and wafers with 10 um, 30 um and 60 um epitaxial layers were evaluated. The wafers with 10 um and 30 um epilayers were virtually free of BPDs, while BPD concentrations of the wafers with 60 um were too high for commercial use.  Concentrations of inclusions, micropipes and trapezoids were also evaluated. Most of the wafers had acceptable levels of these defects, but device yield would be improved by more consistently having low concentrations.

Defects in 4H-SiC Epilayers That Affect Device Yield and Reliability

The electron trapping in gate oxides of m-plane SiC-MOS capacitors were studied by electron injection. The trapped electron densities calculated using the flat-band voltage shift were analyzed. There are possibly three types of electron traps with different capture cross sections. The oxide grown by LPCVD has slightly lower electron trap density than the oxides by thermal oxidation or TEOS-PECVD. The obtained trapped electron densities were found to be one order of magnitude higher than that of Si-MOS and there may be large room for improvement of the electron trap in the gate oxide of SiC-MOSFET for better VT reliability.

Characterization of Electron Traps in Gate Oxide of SiC MOS Capacitors

Output power and efficiency of millimeter-wave power amplifiers depend directly on transistor reliability considerations, perhaps more strongly for CMOS-SOI than for any other device technology.  PMOS, in comparison to nMOS, has potential reliability advantages due to 1) higher energy barrier to the gate dielectric from the valence band than from the conduction band; 2) lower impact ionization rate for holes than for electrons at a given electric field; 3) lower channel leakage and parasitic bipolar transistor gain in partially depleted pFETs.  As a result, voltage-handling limits due to hot carrier injection and time-dependent dielectric breakdown are relaxed.  pMOS 28GHz power amplifier ICs which have performance comparable to or better than nMOS are described,  and short-term reliability tests for the amplifiers which show preliminary reliability benefits are presented. 

Reliability of CMOS-SOI power amplifiers for millimeter-wave 5G: the case for pMOS

The advent of Artificial Intelligence (AI) and big data era brought an unprecedented (and ever growing) need for fast and energy efficient computation that cannot be obtained with the classical von Neumann computing architecture. This paved the way to new technologies that try to mimic the human brain to leverage its energy efficient and distributed computing. Non-volatile memory technologies seem to be the ideal solution for the hardware implementation of artificial neurons and synapses of Neural Network (NN) architectures and have been extensively investigated in the last years. However, they often suffer from limited linearity and symmetry, poor retention, and high variability, thus requiring significant advancements for their mass adoption in NNs. One of the cornerstones on which the required efforts must be based is certainly represented by device simulations, which can be effectively used to achieve a full understanding of the physics governing the device, which in turn is a pre-requisite for their design, optimization and successful exploitation in neuromorphic applications. In this scenario, we focus on Transition Metal Oxide (TMO)-based RRAM, Ferroelectric Tunnel Junctions (FTJ) and 3D-NAND Charge Trap devices and use simulations to address key issues related to neuromorphic operation (linearity and asymmetry) and reliability (variability and retention).  

Premium content

RF Reliability of CMOS-Based Power Amplifier Cell for 5G mmWave Applications

Downloads

Next from IRPS 2022

Electron-assisted switching in FeFETs: MW dynamics – retention - trapping mechanisms and correlation

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES