United States

Design of reliable and high-performance RF power amplifiers in CMOS technologies is becoming more challenging due to the increasing reliability issues as we approach the scaling limit. To provide insight on hot-carrier injection (HCI) degradation at RF frequencies, this paper presents a comprehensive analysis to study this effect on different PA architectures based on their mission profile with a quasi-static approach. Sensitivity analysis on power amplifier RF performance is also discussed to offer a better understanding on the importance of accurate device and aging behavior modeling. 

IRPS 2022 Main Conference 

Comprehensive Analysis of RF Hot-Carrier Reliability Sensitivity and Design Explorations for 28GHz Power Amplifier Applications

rf reliability

hot-carrier degradation

power amplifier

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

technical paper

Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.

Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators

We investigate the impact of charge-trapping on ferroelectric (FE) switching and its influence on memory window (MW) and retention of FeFET. Fabricated FinFETs with ferroelectric gate stack were used to study defects properties (within HZO), trapping/FE-switching interplay, and dynamics. Starting from the electronic-assisted nucleation of FE domains, we investigated the interface charging and degradation, as well as their impact on the polarization compensation, MW and stabilization of the retention. Finally, a balance between those competing processes was analyzed and a retention model of FeFET (capturing behavior over device’s lifetime) was developed 

Electron-assisted switching in FeFETs: MW dynamics – retention - trapping mechanisms and correlation

In SOT-MRAM, the writing path is decoupled from the reading path and therefore considered robust against MgO breakdown in the MTJ. At operation, high current densities flow through the thin metallic SOT layer underneath the MTJ. We find that the SOT track is robust against electromigration, but we observe failure of the MTJ. A thorough chemical analysis indicates the activation of diffusion mechanisms that degrade the free layer and MgO tunnel barrier.

MTJ degradation in SOT-MRAM by self-heating-induced diffusion

Ovonic Threshold Switching Selector faces challenges of VTH stability in intensive applications due to relaxation and the degradation upon endurance cycling. This work investigates the first fire (FF) voltage effects and mechanisms related to the switching characteristics on GeCTe-based selectors. Higher VTH stability and more uniform Ioff-VTH control during endurance cycling were achieved by higher FF design. A power-law model with strong correlation between endurance and pulse-energy was also demonstrated in this study.

Investigation of First Fire Effect on VTH Stability and Endurance in GeCTe Selector

Temperature dependence of charge capture and emission in HfO2 and ferroelectric doped HfO2 are examined over a wide temperature range. Sizeable threshold voltage (Vth) instabilities are observed under cryogenic conditions, contrary to expectation of Arrhenius-based defect freeze-out. The observed data is modelled with the ultra-fast defect levels, located close to the silicon channel. The impact of these traps at room temperature on ferroelectric devices is significant: capture and emission times lie in the range applied for device operation, and can explain the read-after-write delay incorporated in Si-based ferro (FE-)FET operation. 


Modelling ultra-fast threshold voltage instabilities in Hf-based ferroelectrics

Power device characteristics are affected by X-rays used during the inspection of power modules. In this study, the effects of materials and structures of power MOSFETs on the overall degradation were analyzed by irradiating Si MOSFETs and SiC MOSFETs with X-rays using a commercial inspection system. In addition, the effectiveness of thermal and gate voltage annealing was investigated for the irradiated devices. The experimental results confirmed the high radiation tolerance of SiC MOSFETs. In addition, the irradiated devices exhibited difficulty in recovering the shifted threshold voltage without compromising the reliability of the device, indicating that the effects of degradation persisted for a long time.

Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Its Recovery

Forty nine silicon carbide 150 mm wafers from three commercial vendors to be used for fabricating MOSFETs were examined by UVPL imaging to count their concentration of basal plane dislocations, inclusions, micropipes and trapezoids. The wafers were from three vendors, and wafers with 10 um, 30 um and 60 um epitaxial layers were evaluated. The wafers with 10 um and 30 um epilayers were virtually free of BPDs, while BPD concentrations of the wafers with 60 um were too high for commercial use.  Concentrations of inclusions, micropipes and trapezoids were also evaluated. Most of the wafers had acceptable levels of these defects, but device yield would be improved by more consistently having low concentrations.

Defects in 4H-SiC Epilayers That Affect Device Yield and Reliability

The electron trapping in gate oxides of m-plane SiC-MOS capacitors were studied by electron injection. The trapped electron densities calculated using the flat-band voltage shift were analyzed. There are possibly three types of electron traps with different capture cross sections. The oxide grown by LPCVD has slightly lower electron trap density than the oxides by thermal oxidation or TEOS-PECVD. The obtained trapped electron densities were found to be one order of magnitude higher than that of Si-MOS and there may be large room for improvement of the electron trap in the gate oxide of SiC-MOSFET for better VT reliability.

Characterization of Electron Traps in Gate Oxide of SiC MOS Capacitors

Output power and efficiency of millimeter-wave power amplifiers depend directly on transistor reliability considerations, perhaps more strongly for CMOS-SOI than for any other device technology.  PMOS, in comparison to nMOS, has potential reliability advantages due to 1) higher energy barrier to the gate dielectric from the valence band than from the conduction band; 2) lower impact ionization rate for holes than for electrons at a given electric field; 3) lower channel leakage and parasitic bipolar transistor gain in partially depleted pFETs.  As a result, voltage-handling limits due to hot carrier injection and time-dependent dielectric breakdown are relaxed.  pMOS 28GHz power amplifier ICs which have performance comparable to or better than nMOS are described,  and short-term reliability tests for the amplifiers which show preliminary reliability benefits are presented. 

Reliability of CMOS-SOI power amplifiers for millimeter-wave 5G: the case for pMOS

The advent of Artificial Intelligence (AI) and big data era brought an unprecedented (and ever growing) need for fast and energy efficient computation that cannot be obtained with the classical von Neumann computing architecture. This paved the way to new technologies that try to mimic the human brain to leverage its energy efficient and distributed computing. Non-volatile memory technologies seem to be the ideal solution for the hardware implementation of artificial neurons and synapses of Neural Network (NN) architectures and have been extensively investigated in the last years. However, they often suffer from limited linearity and symmetry, poor retention, and high variability, thus requiring significant advancements for their mass adoption in NNs. One of the cornerstones on which the required efforts must be based is certainly represented by device simulations, which can be effectively used to achieve a full understanding of the physics governing the device, which in turn is a pre-requisite for their design, optimization and successful exploitation in neuromorphic applications. In this scenario, we focus on Transition Metal Oxide (TMO)-based RRAM, Ferroelectric Tunnel Junctions (FTJ) and 3D-NAND Charge Trap devices and use simulations to address key issues related to neuromorphic operation (linearity and asymmetry) and reliability (variability and retention).  

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Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators

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