United States

ADC circuits may cause RTS column signatures in 3D stacked CMOS image sensors. This work proposes a statistical and design evaluation of RTS for 40nm node devices, used in ADC circuits. A transistor array mimicking 3T CIS pixel array architecture is used for RTS characterization, with a proposed RTS detection methodology and counting. The designs presented exhibit a noteworthy decrease in the number of RTS occurrences, as evidenced by the experimental results.

IRPS 2024 Main Conference

Design Techniques Evaluation to Mitigate RTS Noise Effect in Column ADC of 3D Stacked Image Sensors

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#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

As ESD design window shrinks, even GOX degradation before hard breakdown during component-level CDM qualification can cause reliability issues such as soft-failures. This study analyzes CDM-induced bias temperature instability (BTI)-like degradation and models threshold voltage (Vth) shift using a very-fast transmission line pulse (VF-TLP), generally proposed for CDM evaluation. Finally, the Vth shift model considering statistical variation is presented. This model can be a guideline to prevent CDM-induced GOX degradation at the early design stage.

An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology

We present HBp-index, a novel quantitative model that explains the combination effect of hydrogen and process heat on peripheral transistors in 3D NAND flash memory. We observed the index linearly matched with the change of electrical characteristics of the transistors for various heat processes. Furthermore, we found the NBTI life time of the peripheral transistors increased by 90mV, which is due to the expansion of the poly-depletion region by increasing hydrogen concentration during cell fabrication.

A Novel Quantitative Model for Combination Effects of Hydrogen and Process Heat on Peripheral Transistors in 3D-NAND Flash Memory

The effect of Off-state stress on a propagation delay (tPD) and a data-valid window (tDV) was characterized. The Vth reduction of PMOSET due to the electron trapping into the nitride in the STI, resulting in the decrease of tDV. The extracted time slope of ∆Vth and ∆tDV showed same ~0.4. It indicates that the degradation was dominated by the off-state stress. The mechanism was investigated by varying the process, and an empirical model was proposed.

Effect of Off-State Stress on Data-Valid Window Margin for Advanced DRAM using HK/MG Process Technology

We report a non-monotonical temperature dependence of hot carrier injection (HCI) degradation for 14 nm Si FinFETs operated at low temperature (LT). An HCI model including multiple-particle single-particle and oxide traps was proposed to separate the effects from different traps. As stress time increases, the dominant traps switched from single-particle traps to oxide traps, and as temperature reduces, oxide traps and single-particle traps will make more contributions to the HCI degradation.

Low Temperature Characterization and Modeling of Hot Carrier Injection in 14 nm Si FinFET

In this work, for the first time, we report an electric-field coupled molecular dynamics to investigate the impact of electric-field and Joule’s heating at an atomic level in 2D-monolayer MoS2. The results indicate a breakdown vulnerability in zigzag direction at a lower electric-field than in armchair direction under similar conditions. Moreover, it is observed that a high-voltage ramp rate (dV/dt) and Joule’s heating enhance tensile-strain of Mo-S bonds which further lowers breakdown field of MoS2.

P71.TX -Electric Field Coupled Molecular Dynamic Insights into Anisotropic Reliability Issues of Monolayer MoS2 Based 2D FETs

In this work, the impact of hot carrier degradation (HCD) variability on N-FETs and static random-access memory (SRAM) cells in different lightly doped drain (LDD) implantations is investigated. It is found that the stress-induced traps increase the VT fluctuation and that the inconsistent current degradation rate contributes to suppressing ID fluctuation. Higher LDD implantation results in lower HCD variability attributed to the weakening of the cluster effect. The mechanisms are explained by calibrated TCAD simulation.

Impact of Lightly Doped Drain on Hot Carrier Degradation Variability in N-FETs and SRAM Cells

We reveal, for the first time, a comprehensive physical insight into high-field electrical breakdown in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs. Electrical, optical, and electro-optic properties of 2D TMD FETs are extensively analyzed in the FETs operated in the non-destructive breakdown regime. Careful investigations reveal that hot carrier electroluminescence (EL) observed in the devices operated at the verge of breakdown can have two distinct origins.

Hot Carrier Dynamics and Electrical Breakdown Analysis in 2D Transition Metal Dichalcogenide FETs

This paper proposes an automated RTN analysis including the detection and identification of number of traps based on non-Gaussian nature of RTN. In addition, we improve the efficiency of HMM algorithm through an adaptive model, achieving over 10 times faster performance compared to conventional method. Finally, we incorporate the impact of RTN into the reliability model by utilizing the OMI. This integration allows for circuit simulations in SPICE, facilitating the design of robust circuits.

A New Method of Automatic Extraction of RTN and OMI-friendly implementation

This paper leverages efficient defect separation technology to model and characterize PBTI in nFinFETs with advanced nodes. Two types of traps are identified, including Type-Be1 and Type-Be2, which can be well described by three-state NMP theory. Type-Be2 is in the IL layer and may originate from Vo or HB in SiO2. Type-Be1 is in the HK layer but its origin is still unclear. Finally, the impact of PBTI on circuit performance is also assessed.

Investigation of Positive Bias Temperature Instability in advanced FinFET nodes

A typical automotive or industrial end equipment system consists a multitude of analog, power and mixed signal ICs. These ICs are fundamentally driven by similar underlying vectors such as increasing performance and capability while reducing size and cost and maintaining or enhancing reliability.
The talk will focus on key analog and power component careabouts and reliability mechanisms that are critical for scaling these components and also discuss advances in technology and component design that enable scaling while achieving the required technology reliability.

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Design Techniques Evaluation to Mitigate RTS Noise Effect in Column ADC of 3D Stacked Image Sensors

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An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology

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