United States

As ESD design window shrinks, even GOX degradation before hard breakdown during component-level CDM qualification can cause reliability issues such as soft-failures. This study analyzes CDM-induced bias temperature instability (BTI)-like degradation and models threshold voltage (Vth) shift using a very-fast transmission line pulse (VF-TLP), generally proposed for CDM evaluation. Finally, the Vth shift model considering statistical variation is presented. This model can be a guideline to prevent CDM-induced GOX degradation at the early design stage.

IRPS 2024 Main Conference

An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology

very fast transmission line pulse(vf-tlp)

bias temperature instability(bti)

charged device model(cdm)

electrostatic discharge(esd)

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

We benefit from the statistical characterization of Off-State Stress (OSS) on nanoscale devices to better understand the competing charge trapping effects. We show that OSS in such devices manifests a turn-around behaviour caused by the competition of hole injection into oxide defects, which dominates for shorter times, and interface state generation, which gains relevance for longer times. For this, we analyze the evolution of different parameters (Vth, Isub, gm) along time at different stress conditions.

Statistical characterization of off-state stress degradation in planar HKMG nFETs using device arrays

On-chip sensors are a key tool in characterizing wear-out processes in semiconductors. We present a novel sensor design that can separably monitor transistor wear-out under BTI and HCI stress regimes in both NMOS and PMOS transistors and that allows for DC read-out. The design is implemented in a 12nm FinFET process and subjected to 1500 hours of stress to verify the sensor and provide insights into scaled CMOS degradation behaviours.

A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process

In this paper, we have monitored the cycle-to-cycle variation (CCV) of ultra-scaled FinFETs during HCD and BTI stress. Different measurement speeds have been utilized to separate the intrinsic CCV from the stress-induced CCV. Statistical of nFinFETs shows under the same amount of ΔVth, PBTI induces a larger dynamic variability than HCD. Surprisingly, pFinFETs with under much Vth degradation show only a little Vth variation, suggesting its less sensitivity to stress-induced CCV.

Impact of Hot Carrier Degradation and Bias Temperature Instability on GHz Cycle-to-cycle Variation in Ultra-scaled FinFETs

Self-heating of ultra-scaled system-on-chips is becoming a severe challenge in the electronic industry, which demands a fast on-chip heat-spreading solution. Graphene is predicted to be a potential heat spreader due to its high thermal conductivity. However, low cross-plane thermal conductivity of graphene with metal is a serious concern.  This work, for the first time, proposes and demonstrates a unique orbital overlap engineering solution to enhance the phonon coupling of graphene with a hot spot source. 

Breakthrough Metal/Graphene Interface Phonon Engineering for Reliable Graphene Based-Heat Spreaders

This works presents a 5-V tolerant supply clamp for ESD protection in 16nm FinFET technology. Active feedback is employed to enable a very small RC time constant (4 ns) used in the timer circuit. The small RC time constant makes the clamp robust to unwanted triggering during fast power ramp-up, while the feedback circuit sustains the clamp on for the entire duration of a 2-kV HBM event.

Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology

During CDM ESD events, MOSFET gate oxides may be exposed to high voltage stress for a few hundred picoseconds, and the gate oxide breakdown voltage is important for ESD designers. This work presents an on-chip pulse generator capable of producing clean pulses with amplitude up to 6 V and pulse width as short as 200 ps. The pulse generator is used for an experimental investigation of gate oxide breakdown voltage on a sub‑ns timescale.

On-Chip Single-Shot Pulse Generator for TDDB Characterization on a Sub-nanosecond Timescale

We characterize the reliability of BEOL dielectrics between two metal tips using a design-representative test structure. To distinctively study the different failure modes, being line-to-line, via-to-line and tip-to-tip breakdown, an experimental test procedure called “double V-ramp stress” is proposed. By analyzing the leakage currents at different terminals under 4-point voltage stress, the different failure modes can be identified electrically. Our results confirm that the tip spacing control is pivotal for the tip-to-tip dielectric reliability.

BEOL tip-to-tip dielectric reliability characterization using a design-representative test structure

3D packaging (or more generally Heterogenous Integration through advanced packaging innovations) are increasingly necessary to deliver power, performance, area, cost, and time-to-market (PPACT) benefits to remain competitive in the high-performance semiconductor industry [1],[2]. In this talk, the focus is on reliability challenges and opportunities that are amplified because of complex heterogeneously integrated 3D packaging architectures using two examples from AMD’s recent collaboration with U.S. Department of Energy in designing Frontier and El Capitan.

2.5D/3D Packaging and Reliability: New Frontiers, Old Paradigms, and Opportunities

In this paper, a thermal analysis of a server SoC is performed, considering a realistic layer stack configuration mounted on a printed circuit board (PCB) with an active heat sink for the cooling solution. We investigated the impact of the heterogeneous power distribution within the SoC cluster. This paper also reports the thermal transients with workload conditions, which lead to improvement in thermal reliability and performance by ~26% of the proposed A10 node server SoC.

Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies

In this work the impact of cryogenic temperatures on latchup in 28 nm planar bulk CMOS technology is discussed. Measurement and simulation results indicate that at low temperatures the wells sheet resistances increase more that 50% which can lead to increased latchup risk. However, our results show that the current gain product of the parasitic bipolar transistors reduces with cryogenic temperatures that can compensate LU risk.

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An Analysis of CDM-induced BTI-like Degradation using VF-TLP in Advanced FinFET Technology

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Statistical characterization of off-state stress degradation in planar HKMG nFETs using device arrays

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