United States

This paper reports on the high temperature (HT) robustness of enhancement-mode (E-mode) p-GaN-gated AlGaN/GaN high electron mobility transistors (HEMTs), with an emphasis on the key transistor-level parameters for digital and analog mixed-signal applications. In-situ measurements from room temperature (RT) to 500 °C show that trends in Vth, RON, ID,max and IG,max are largely as expected based on firstorder changes in the semiconductor properties. The fabricated transistors exhibited stable performance over 20 days at 500 °C. To the best of the authors’ knowledge, this work is the first systematic study on the HT performance of E-mode p-GaN-gated AlGaN/GaN HEMTs, and sheds light on their use in mixed-signal and low-voltage power circuits.

IEEE WiPDA 2022

High Temperature Robustness of Enhancement-Mode p-GaN-Gated AlGaN/GaN HEMT Technology

longterm survival

transistor

p-gan

high temperature

**BRACIS** originated from the combination of the two most important scientific events in Brazil in Artificial Intelligence (AI) and Computational Intelligence (CI): the Brazilian Symposium on Artificial Intelligence – **SBIA** (22 editions), and the Brazilian Symposium on Neural Networks – **SBRN** (13 editions). **ENIAC** is a national forum for researchers, practitioners, educators and students to present and discuss innovations, trends, experiences, developments and work in progress in the fields of Artificial and Computational Intelligence. **STIL** is the bi-annual Language Technology event.
All events are supported by the Brazilian Computer Society – Special Interest Groups: **CE-IA**, **CE-IC** and **CE-PLN**.

To access the 10th Brazilian Conference on Intelligent Systems (**BRACIS**), you need to register for the conference.  Please visit the Conference official site to register

[Register now](http://c4ai.inova.usp.br/bracis2021/)

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BRACIS 2021

BRACIS originated from the combination of the two most important scientific events in Brazil in Artificial Intelligence (AI) and Computational Intelligence (CI): the Brazilian Symposium on Artificial Intelligence – SBIA (22 editions), and the Brazilian Symposium on Neural Networks – SBRN (13 editions). 
ENIAC is a national forum for researchers, practitioners, educators and students to present and discuss innovations, trends, experiences, developments and work in progress in the fields of Artificial and Computational Intelligence. 
STIL is the bi-annual Language Technology event.
All events are supported by the Brazilian Computer Society – Special Interest Groups: CE-IA, CE-IC and CE-PLN

technical paper

Download the proceedings [here](https://underline.io/events/372/lounge)
 
 
 The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.
 
 **Topics of interest**
* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency Or Compact Converters
* Safe Operating Areas Of Wide Bandgap Devices, including Short Circuit, Spike, &Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Hard-Switched & Soft-Switched Application Analysis
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, Grid Power Systems, Space and Aerospace
* Wide Bandgap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging

You must register to attend this event. If you haven't done so already, please use the link below to register for the event. All registered attendees will have access to the event site on November 4th.

Registration Is Required

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

In this work, the influence of various oxide electric field (۳ܠܗ (stress conditions on the gate oxide lifetime, gate leakage current, and threshold voltage of 1.2 kV 4H-SiC power planar metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. The results suggest that high ۳ܠܗ stress (> 9.4 MV/cm) applied to the gate oxide of commercial SiC power MOSFETs for a certain period degrades the oxide lifetime due to high Fowler-Nordheim (F-N) electron tunneling current followed by hole trapping. Moreover, hole trapping enhances the gate leakage current and reduces the threshold voltage. Therefore, the generation of holes under high electric field conditions should be avoided to ensure the reliability of SiC power MOSFETs.

Effects of Oxide Electric Field Stress on the Gate Oxide Reliability of Commercial SiC Power MOSFETs

瀆 It has been demonstrated that basal plane dislocations (BPDs)-induced stacking faults (SFs) cause body diode degradation in commercial 4H-SiC power MOSFETs, especially with higher voltage ratings. BPDs originate from 4HSiC boule, epi growth, and ion implantation. Considering the lower cost of ion implantation at room temperature (RT), this work investigates the potential of RT ion implantation replacing heated (HT) ion implantation by comparing the influence of both ion implantations on the body diode degradation of commercial 3.3 kV 4H-SiC power MOSFETs. We demonstrate with long-term (up to 1000 hours) forward current stress that RT implantation can keep the body diode degradation of 3.3 kV 4H-SiC power MOSFETs within the specification limits compared with HT implantation.

A Comparison of Ion Implantation at Room Temperature and Heated Ion Implantation on the Body Diode Degradation of Commercial 3.3 kV 4H-SiC Power MOSFETs

This paper presents a comparison of 1.2 kV 4H-SiC MOSFETs and Ti JBSFETs with deep P-well structures. For a fair comparison of the short-circuit characteristics between the MOSFETs and JBSFETs, an innovative design approach for the JBSFETs was implemented to obtain the same specific on-resistance to the MOSFETs. To improve the short-circuit characteristics of the MOSFETs and JBSFETs, channeling implantation was conducted to form a deep P-well structure, that helps reduce the maximum saturation current during the shortcircuit event. Using this approach superior short-circuit characteristics are achieved in the MOSFETs and JBSFETs. However, the JBSFETs provide a shorter shortcircuit withstand time than the MOSFETs due to the high leakage current from Schottky contact. Sentaurus 2D TCAD was used to understand and clarify the short-circuit mechanisms of the MOSFETs and JBSFETs. It was discovered that the MOSFETs failed due to the high current in the channel region, but the failure of JBSFETs happens in the Schottky contact. Moreover, solutions to improve the short-circuit characteristics of the JBSFETs are proposed; a narrow Schottky width and high work function metal.

A Comparison of Short-Circuit Failure Mechanisms of 1.2 kV 4H-SiC MOSFETs and JBSFETs

Neutron-induced failures in power electronics are a source of concern in many high-reliability applications. This paper describes how to estimate the device's decreased lifetime expectancy based on its usage. The physical mechanism, Failure in Time (FIT) statistics and FIT rate calculation methodology are presented. Several Microchip SiC MOSFETs and Schottky barrier diodes at different voltage ratings were tested, and the results for the excess FIT rate calculation based on various factors such as operation voltage, altitude, device area, latitude, and duty factor are presented.

Failure Rate Calculation Due to Neutron Flux with SiC MOSFETs and Schottky Diodes

The same core device model is shown to accurately reproduce the current-voltage and capacitance-voltage characteristics of enhancement-mode GaN 100 V power transistors of various sizes. Using linear scaling, excellent agreement with measurements is achieved over an order of magnitude variation in total gate width. Fractional variation in onresistance is shown to decrease with increasing transistor size, with implications for integrated circuit-sized transistors where gate width decreases by up to 5 orders of magnitude.

Scaling of EPC’s 100 V Enhancement-Mode Power Transistors

In this paper, we discuss how advancements in the integration of gallium nitride (GaN) power ICs leads to faster switching, higher efficiencies, simplifier designs and improved reliability. Navitas’ integrated GaNSense™ technology features provide real-time sensing and protection to achieve these new levels.

Advancement in Integration for GaN Power ICs

In this study, the impact and correlation of drainand gate-voltage stress on the threshold voltage of commercially available p-gate GaN HEMTs are investigated. This is based on single-pulse measurements acquired with a custom pulse setup, thus the transient behavior can be determined and subsequently translated into dc characteristics. As a novelty, measurements of the threshold voltage for short-circuit stress of up to 600 V are shown. As a result, a constant threshold voltage shift is observed for on-state drain-voltage stress, while off-state drain-voltage and gate-voltage stress lead to a threshold voltage instability. Finally, drain stress and gate stress appears to superimpose, consequently already application-relevant gate-driving conditions show a drastic impact of the short-circuit capability.

Threshold Voltage Behavior and Short-Circuit Capability of p-Gate GaN HEMTs Depending on Drain- and Gate-Voltage Stress

To reduce global warming / human health impacts, governments around the globe have been committed to reduce greenhouse gas and pollutant emissions.  To achieve these goals, vehicles with internal combustion engines (ICEs) are being replaced at very fast pace by vehicles with electrified power trains, (e.g., battery-electric vehicles (BEVs), plug-in hybrid electric vehicles (PHEVs), fuel-cell electric vehicles (FCEVs), etc.) To offer electrified functions, many power-electronic (PE) modules are incorporated on these vehicles (e.g., traction inverters, DC/DC converters, on-board / off-board chargers, etc.)  In these PE modules, WBG devices have shown promising potentials replacing Si ones to achieve better performance, smaller footprints, lighter weights, etc.  However, from many view angles, many WBG products are working under higher stresses than the Si ones to deliver better performance, leading to concerns of lower long-term reliability / higher parameter drifts.  To convince automotive manufacturers / suppliers, WBG vendors should disclose the raw-wafer / epi-layer defect info (e.g., densities, failure mechanisms, long-term aging effects, etc.), quality assurance processes and qualification results, EOL screening processes and pass/fail criteria, production yields, test-to-failure data (e.g., Weibull charts, bath-tub curves), and actual field return results.  For comparison, Si experience will be shared in this presentation.

Reliable wide-bandgap (WBG) products for safety-critical automotive applications – what are expected

GaN power devices have been in mass production for over 12 years [1] and have arguably crossed over the tipping point in adoption with such end-uses as cell phone fast chargers, DC-DC converters for servers, motor drives for electric bicycles and scooters, class-D audio amplifiers, and lidar sensors for autonomous vehicles and robots.  Some of these applications first started using discrete GaN transistors and later converted to GaN integrated circuits.  Others have stayed with discrete devices.  This paper will discuss the reasons for different adoption rates in different applications and will speculate on the changes that will occur due to new GaN transistor performance and new capabilities in integrating functions in GaN.

What is the Right Level of Integration for GaN Power Devices?

Our world’s sustainable future is linked to energy efficiency and GaN’s innovative technology. The world is witnessing a data explosion. The demand for a cleaner and healthier global environment clearly shows that sustainability must be more than a footnote in a company’s annual report. Yet, the energy-driven world is leading to historically high-power consumption due partly to our increased dependence on power-reliant industries, including data centers, electric vehicles, renewable energy systems, and consumer electronics. Technology helped create this problem. Now, it’s time for technology – specifically ‘GaN-Powered’ technology – to help solve this problem. From the humble chargers to the all-important EV powertrain, GaN power systems are solving today’s technical, economic, and environmental challenges. During this session, Jim Witham, CEO of GaN Systems, will discuss how GaN plays a crucial role in changing our relationship with power by enabling the creation of new sustainability solutions.

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Effects of Oxide Electric Field Stress on the Gate Oxide Reliability of Commercial SiC Power MOSFETs

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How to Generate Synthetic Paintings to Improve Art Style Classification

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