United States

IRPS 2022

Silicon Lifecycle Management: Increasing Semiconductor Predictability in an Unpredictable World

keynote

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**PROGRAM AT A GLANCE:**
 

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**2022 IEEE International Reliability Physics Symposium has gone mobile!**

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Channel percolation in Ferroelectric FET (FeFET) due to random spatial distribution of switched domains reduces the number of accessible threshold voltage (VTH) states, thus posing a profound reliability challenge for neuromorphic. However, channel percolation is not universally present in FeFET and only exists when the channel regions underneath the domains have negligible interaction. In this work, we perform a comprehensive evaluation on the parameters that impact neighbor interaction, and hence channel percolation. We reveal i) weak gate control with thick ferroelectric layer enhances neighbor interaction and suppresses percolation; ii) higher temperature can also reduce percolation by weakening the gate control. 

Supressing Channel Percolation in Ferroelectric FET for Reliable Neuromorphic Applications

In this work, we demonstrate that proper engineering of VTH in ferroelectric FET is necessary to ensure correct array operation for in-memory computing applications. We highlight that for all current-based computing operations, it is necessary to keep both the low-VTH and high-VTH states positive to cut off the leakage for grounded unselected cells. To reach that design target, we systematically evaluate various design options for VTH engineering, including the gate metal work function, the body bias, and the buried oxide thickness, using calibrated TCAD. We establish the design guidelines for VTH engineering to ensure the successful operation of in-memory computing.

Ferroelectric FET Threshold Voltage Optimization for Reliable In-Memory Computing

We present an analysis of the impact of passivation and gate foot etching on the reliability and trapping behavior of RF GaN HEMTs. The study is based on HTRB experiments and DCT analysis.  We demonstrate that: passivation significantly impacts on the stability of the gate-leakage characteristics during HTRB stress; best stability is obtained through the use of LPCVD. DCT measurements reveal the presence of two trapping processes;  the slower time constant depends on the processing parameters and increases in presence of optimized gate-foot etch and passivation. The results presented provide information for the optimization of GaN RF devices.

GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse

For plasma process induced damage (PID) qualifications stresses are necessary to detect lifetime reduction risks. JEDEC JEP001 requires HCS, BTS, and TDDB stresses, or a revealing stress for this detection. Due to the large number of devices that should be tested the revealing stress can be preferable. This paper reviews the two main options for the revealing stress for thick oxides, constant gate current (CGC) versus constant gate voltage (CGV) stresses. The results are also intended as input to the discussions in the current JEDEC 14.2 PID standard working group.

Revealing stresses for plasma induced damage detection in thick oxides

IoT edge devices are expected to have high-capacity and low-power storage memory, as well as smart data processing capability such as machine learning and AI, to fully utilize big-data by co-working with cloud computing system. Such edge intelligence requires energy-efficient data movement and computation, which opens new challenges and opportunities to integrated devices, circuits and systems. In this paper, we introduce monolithic 3D integration technologies of (1) high-density embedded memory and (2) in-memory computing, both of which are enabled by oxide semiconductor FETs and memory devices, for AI acceleration. We address key reliability issues regarding manufacturability for each technology. 

Reliability characteristics of mobility-enhanced FET and wakeup-free ferroelectric capacitor enabled by InGaZnO for machine-learning accelerator in AI chip

Reliability research is shifting from from devices to circuits. Wide range of operating conditions and different scaling factors for reliability modes presents a unique challenge to predict circuit lifetime. We present the “Q&amp;R on Chip” (QROC), a unified, oven-less and scalable platform for circuit reliability evaluation. State-of-the-art QROC chips helps evaluate various modes such as aging, gate-oxide breakdown and thermal reliability.  A new test platform with an on-board FPGA, PC interface and heater socket for temperature control is designed. Preliminary aging stress data from more than 15000 instances of ring-oscillators comprised and 107 different RO is presented.

On-Chip (QROC): A Unified, Oven-Less and Scalable Circuit Reliability Platform

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper introduces a modified methodology for conducting OSS in scaled tri-gate devices at accelerated conditions that avoids artifacts associated with punch-through while enabling reliability risk assessment. The methodology is validated for both NMOS &amp; PMOS devices and provides consistent degradation mechanism. Finally, it is shown that on-state gate-oxide TDDB remains the reliability limiter compared to OSS TDDB. 

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Silicon Lifecycle Management: Increasing Semiconductor Predictability in an Unpredictable World

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Supressing Channel Percolation in Ferroelectric FET for Reliable Neuromorphic Applications

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