United States

This poster presents our work on rapid simulation and automated design of silicon photonics devices funded by the NSF under a CRII grant. Silicon Photonics is an exciting emerging technology platform which leverages existing CMOS Silicon-on-Insulator foundry infrastructure to guide and manipulate light on the nanoscale. Despite having great potential, silicon photonic devices are challenging to design and simulate due to the lack of analytical solutions, small wavelengths, and large structures involved. Simulations today rely on the Finite-Difference Time-Domain (FDTD) method. Unfortunately, FDTD suffers from slow convergence, poor accuracy, long simulation times, and significant numerical dispersion. The goals of this project are to couple a fast simulation method with optimization techniques to achieve rapid automated design of silicon photonics devices. To achieve this, we propose an alternative simulation approach which is based on boundary integral equations (BIE) in the frequency-domain. Our method is dispersion-free and only requires discretization of the material interfaces which reduces the number of unknowns significantly. The method is high-order accurate, achieving close to spectral accuracy, and only requires meshing at a few points per wavelength. Our poster introduces our BIE algorithms and implementations in both two and three dimensions and demonstrates recent results using our framework to rapidly simulate silicon photonic devices with high accuracy. We also demonstrate fast automated design of new, high-performance silicon photonic devices in both 2D and 3D by applying the adjoint method for computing the gradient of the objective function used for optimization. We have fabricated several of the devices optimized via our methodology and are currently in the process of measuring them to compare against our predicted simulation results. 

https://underline.io/speakers/59501-constantine-sideris




NSF Workshop on Micro/Nano Circuits and Systems Design

CRII: SHF: Ultra-fast Simulation and Automated Design of Silicon Photonics Devices

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

ESSCIRC ESSDERC Educational Events

The Educational Events of ESSCIRC ESSDERC 2021. 

poster

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


Associative Processing (AP) is a promising alternative to the Von Neumann model as it addresses the memory wall problem through its inherent in-memory computations. However, because of the countless design parameter choices, comparisons between implementations of two so radically different models are challenging for simulation-based methods. To tackle these challenges, we develop an alternative analytical approach based on a new concept called architecturally-determined complexity. Using this method, we asymptotically evaluate the runtime/storage/energy bounds of the two models, i.e., AP and Von Neumann. We further apply the method to gain more insights into the performance bottlenecks of traditional AP and develop a new machine model named Two Dimensional AP to address these limitations.

https://underline.io/speakers/59502-jing-li

CAREER: Associative In-Memory Graph Processing Paradigm: Towards Tera-TEPS Graph Traversal In a Box

With the advent of Internet-of-Things and the necessity to enable intelligence in embedded devices like mobile phones, smart watches etc., low-power and secure hardware implementation of neural networks is vital. Despite achieving super-human performance and classification accuracies on a variety of perception tasks, Deep Neural Networks (DNNs) have been shown to be adversarially vulnerable.  A DNN can be easily fooled into misclassifying an input with slight changes of pixel intensities. This vulnerability severely limits the deployment and potential safe-use of DNNs for real world applications such as self-driving cars, malware detection, healthcare monitoring systems etc. This poster investigates hardware aware optimization techniques to potentially resolve or resist software vulnerabilities (specifically, adversarial attacks). It aims to explore the design space of energy-accuracy-robustness trade-ff cohesively with algorithm-hardware co-design to create truly functional intelligent systems. This poster demonstrates robustness aware algorithms broadly applicable to the energy-efficient and secure implementation of DNN engines on both current complementary metal oxide semiconductor (CMOS) accelerator platforms and emerging memory technologies (with analog crossbar dot-product engines).

https://underline.io/speakers/59503-priyadarshini-panda

Enabling Energy-Efficient and Robust Machine Intelligence with Algorithm-Hardware Co-Design

The poster presents thermal and power delivery modeling and co-design considerations for emerging 2.5D/3D ICs.

https://underline.io/speakers/59504-muhannad-bakir

Electrical-Thermal Co-Design of 2.5D/3D ICs

While the proliferation of electronics has been driven by computing and consumer applications for a long time, integrated circuits (ICs) presently undergo accelerated integration into healthcare, transportation, robotics, and autonomous systems. In addition to provision of prescribed functionalities of sensing, computing, and processing, these ICs must meet stringent reliability specifications in order to safeguard performance and safety of the whole mission-critical system where deployed. Circuits designed to be fail-safe by design exhibit low occurrences of failure. However, having a sign of no failure under typical verification and test procedures yields no guarantee for meeting a given near-zero or extremely-low failure specification. On the other hand, exhaustiveness may never be achieved by brute-force failure detection, which results in an unacceptably high cost in simulation and testing. This project will develop efficient machine-learning techniques for extremely-rare circuit-failure detection without needing large amounts of expensive simulation or test data. The proposed techniques will enable cost-effective verification and test of reliability-critical ICs and mission-critical systems in general. The research undertaken will also enable the two groups at UC Santa Barbara and UT Dallas to educate and train undergraduate and graduate students, including women and underrepresented groups, thus expanding the and contributing to the much needed US technological workforce.

It is believed that extracting critical failure information via machine learning within practical limits of available measurement or simulation data can go a long way towards extremely rare failure detection. This project centers on developing an active-learning framework that intelligently samples in the high-dimensional space of complex interacting design parameters, manufacturing variations, and operating conditions, achieving the goal of data-efficient detection of rare circuit failures. The targeted active-learning framework will be supported by the development of machine-learning model foundations and robust learning methods that can scale to high-dimensional parameter spaces. The key objective of this project is to make extremely-rare failure discovery and identification of the underlying failure mechanisms practically viable by extracting the maximum amount of useful information possible from a small amount of available data. The proposed extremely-rare failure discovery work will be broadly applicable to verification and failure analysis of analog, mixed-signal, radio-frequency, and memory circuits with stringent failure specifications and many other types of mission-critical systems.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

https://underline.io/speakers/59522-hanbin-hu

Collaborative Research: SHF: Medium: Data-Efficient Uncovering of Rare Design Failures for Reliability-Critical Circuits

Biological neural networks process streams of temporal information at efficiencies and proficiencies well exceeding those of man-made systems. Recent work in understanding brain dynamics from the point of view of machine learning is starting to demystify the mechanisms behind their extraordinary performance. By distilling these mechanisms in neuromorphic technologies, the prospect of practical brain-like processing at the edge is becoming real. However, the tools at the disposal of neuroscientists and engineers to prototype and train such models are still inadequate. In this poster, I explain the potential rewards and challenges of training biological neural networks, namely Spiking Neural Networks (SNNs). I will provide the roadmap for the solutions to these problems, which build on an exciting combination of autodifferentiation techniques and dynamics inspired by neurobiology. 

https://underline.io/speakers/59505-emre-neftci

Scalable Neuromorphic Learning Machines

Our CAREER research aims to developing novel computing systems exploiting Three-Independent-Gate Field Effect Transistors (TIGFETs), a novel device technology capable of device-level functionalities typically not achievable by standard CMOS and leading to major benefits at gate and circuit levels. A TIGFET is capable of dynamic reconfiguration of its polarity. In order to fully assess the potential of this technology, we are demonstrating: (1) the fabrication, characterization and modeling of TIGFETs using advanced semi-conductor materials, (2) the development of a complete design framework for TIGFETs, including a design kit, novel circuit primitives and dedicated design tools, and (3) the evaluation of TIGFET-enabled systems.

https://underline.io/speakers/59506-pierre-emmanuel-gaillardon

Functionality-enhanced Devices for Extending Moore's Law

Deep neural networks (DNNs) have gained widespread applications in numerous applications, especially for embedded and Internet-of-Things (IoT) devices. Nowadays on-device DNN inference has been extensively investigated because of its inherent advantages on data privacy, response time and bandwidth demand than cloud-based inference. On the other side, on-device DNN learning, which also has very strong practical demands and owns the similar advantages over the cloud-based training, however, has not been widely studied yet due to the dilemma between expensive training cost and limited on-device resource.  To address this challenge and promote the further deployment of on-device learning, this project proposes to leverage low-rank tensors, as a powerful mathematical tool for representing and compressing tensor-format data, to achieve real-time energy-efficient DNN learning on the device. 

https://underline.io/speakers/59507-bo-yuan

TensorNN: An Algorithm and Hardware Co-design Framework for On-device Deep Neural Network Learning using Low-rank Tensors

Machine learning is the key to sustaining the economic growth in many sectors within the U.S. science and engineering enterprise. Neuromorphic architectures that mimic biological neurons and synapses can execute machine learning algorithms in an energy-efficient manner, allowing for their integration with the internet-of-things, another industry sector projected to have an economic impact of more than $1 trillion by 2025. However, neuromorphic architectures are fundamentally unreliable. They introduce errors during execution, limiting the dependability of machine learning and impeding their technological progress. This project will address dependability challenges of neuromorphic computing, by looking at all levels, from building error-resilient machine learning algorithms to designing fault-tolerant hardware. This project will advance the field by 1) making neuromorphic computing reliable, efficient, programmable, and easy-to-use for the community, 2) teaching future science and engineering students how to make machine learning algorithms error-resilient, 3) creating job opportunities in neuromorphic industry through national and international internships and collaborations, 4) raising interest of high school students in STEM through neuromorphic computing enabled robotics workshops, and 5) building an integrated neuromorphic community through a new focused conference on neuromorphic computing.

https://underline.io/speakers/59508-anup-das

Facilitating Dependable Neuromorphic Computing: Vision, Architecture, and Impact on Programmability

We present and investigate a novel application domain for deep reinforcement learning (RL): droplet routing on digital microfluidic biochips (DMFBs). A DMFB, composed of a two dimensional electrode array, manipulates discrete fluid droplets to automatically execute biochemical protocols such as point-of-care clinical diagnosis. However, a major concern associated with the use of DMFBs is that electrodes in a biochip can degrade over time. Droplet-transportation operations
associated with the degraded electrodes can fail, thereby compromising the integrity of the bioassay outcome. We show that casting droplet transportation as an RL problem enables the training of deep network policies to capture the underlying
health conditions of electrodes and provide reliable fluidic operations. We propose a new RL-based droplet-routing flow that can be used for various sizes of DMFBs, and demonstrate reliable execution of an epigenetic bioassay with the RL droplet router on a fabricated DMFB. To facilitate further research, we also present a simulation environment based on the OpenAI Gym Interface for RL-guided droplet-routing problems on DMFBs.

https://underline.io/speakers/60045-krishnendu-chakrabarty

Adaptive Droplet Routing in Digital Microfluidic Biochips Using Deep Reinforcement Learning

Emulating the cognitive abilities of the brain will enable new paradigms in computing not currently accessible with digital architectures. This poster discusses the use of CMOS circuits in conjunction with devices such as resistive memory (memristors) that mimic the complex synaptic learning modalities found in the brain. System level time-dynamics is examined in the context of spatio-temporal pattern recognition. This research will ultimately advance the capabilities of intelligent computers for sensory processing and control, anomaly detection, and inference and outcome prediction.

https://underline.io/speakers/59511-kurtis-cantley

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