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  DRAM vendors today choose to keep the internal topologies of DRAM devices secret.  This decision introduces significant practical challenges for designers of memory controllers who wish to provide their own forms of Rowhammer defenses. This paper describes three such challenges and the vulnerabilities, inefficiencies, and overhead they introduce. Defenses implemented at the memory controller could reduce (if not eliminate) these deficiencies should internal DRAM topology be made available.

IRPS 2022

The Price of Secrecy: How Hiding Internal DRAM Topologies Hurts Rowhammer Defenses

rowhammer

dram

security

technical paper

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This work investigates both avalanche behavior and failure mechanism of 3 kV GaN-on-GaN vertical P-N diodes, that were fabricated and later tested under unclamped inductive switching (UIS) stress. The goal of this study is to use the particular avalanche characteristics and the failure mechanism to identify issues with the field termination and then provide feedback to improve the device design. DC breakdown is measured at the different temperatures to confirm the avalanche breakdown. Diode’s avalanche robustness is measured on-wafer using a UIS test set-up which was integrated with a wafer chuck and CCD camera. Post failure analysis of the diode is done using SEM and optical microscopy to gain insight into the device failure physics.


Study of Avalanche Behavior in 3 kV GaN Vertical P-N Diode Under UIS Stress for Edge-termination Optimization

In this paper, a simple circuit is incorporated in a 650V E-mode GaN HEMT process technology to protect all terminals against ESD stress from any direction. Even in the worst case, the gate subjected to negative ESD pulse with respect to grounded drain, the 650V E-mode HEMT can still pass 5kV HBM.

Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection

The current trend in the automotive industry towards increasingly detailed and more granular mission profiles (MPs) is also giving rise to an enormous number of various MPs, distinguishing each individual application and use case imaginable. To keep an overview in the face of this flood of data, to filter out and select the qualification relevant MPs, and to create a suitable and simply designed reliability requirement, a MP clustering approach using a quantile criterion is presented. This generic approach is universally applicable and therefore not limited to the automotive industry.
Based on equivalent test times (ETTs) and acceleration factors (AFs), after determining the quantile criterion, a representative MP can be selected either from an existing best fit MP or an artificially generated MP, obtained by numerical methods. Furthermore, the coverage of these MP requirements by technology reliability capabilities can be evaluated with ease. This approach is a generic concept and can therefore be applied to all well-known and commonly used damage accumulation and failure acceleration models. In the presented automotive case studies, the temperature accelerated Arrhenius model, multidimensional MPs with temperature and voltage acceleration, the temperature cycling Coffin-Manson model as well as a non-linear damage accumulation model are investigated.

Mission Profile Clustering Using a Universal Quantile Criterion

A physics-based system-level electromigration (EM) modelling platform is employed to simulate EM and its impact on the IR drop from the supply voltage to the standard-cells for a power delivery network design in a 3 nm logic node. The simulated PDN elicited high EM-tolerance. Despite EM voiding in multiple PDN segments, the EM induced IR-drop increase at the standard-cell level stayed below 3.3% without any catastrophic standard-cell failures. Use of ruthenium rails reduced IR-drop penalty of system EM by a factor of ~0.6 compared with copper rails. 

System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents

Reliability testing of modern tantalum capacitors shows the presence of both types, infant mortality (IM) and wear-out (WO) failures. To assure reliable operation, the probability of IM failures should be reduced to below the specified level, and the time of WO inception should be greater than the required useful life of the parts at operation conditions. In this work, several types of MnO2 and polymer cathode tantalum capacitors have been tested at highly accelerated conditions to assess voltage acceleration factors, determine adequate burn-in conditions, and assess the useful life. A modified time dependent dielectric breakdown (TDDB) model has been suggested to explain both types of failure, and a physical mechanism of degradation that is based on migration and reactions of oxygen vacancies explains increase of the defect related, IM failures with the level of stress.

Infant Mortality and Wear-Out Failures in Polymer and MnO2 Tantalum Capacitors

A systematic study of the time-dependent dielectric breakdown of 3D ferroelectric (FE) and antiferroelectric (AFE) Si:HfO2 capacitors is reported. The voltage and temperature acceleration of characteristic breakdown time is studied. The 10 year lifetime extrapolation is projected to be 2.3 MV/cm and 2.7  MV/cm for 20 nm FE and AFE devices respectively. Further, 10 nm AFE devices had projected lifetime at 2.5 MV/cm at 100 °C. The effect of the polarization measurements on the TDDB is studied and the impact to the lifetime extrapolation was found to be minimal.

Reliability of Ferroelectric and Antiferroelectric Si:HfO2 materials in 3D capacitors by TDDB studies

In the advanced technology process, owing to the low and tunable trigger voltage, diode-triggered SCRs (DTSCRs) are widely used in low-voltage applications with extremely narrow electrostatic discharge (ESD) design margins. The breakdown of DTSCRs ESD structure with abnormal leakage current under transmission line pulsing stressing was studied in this work. The physical origins of DTSCRs have been established through failure analysis (FA). The mismatch of the thermal expansion coefficient of local materials results in redundant stress. Such redundant stress induce the structure dislocations and cracks were captured by transmission electron microscopy at atomic scale. A multi-physical simulation is conducted to scrutinize the breakdown transient process.

Nanoscale Analysis of Breakdown Induced Crack Propagation in DTSCR Devices

Reliability qualification of HV interconnects is more complicated due to additional consideration of inter-metal impacts under the influence of HV operation. Unlike intra-metal structure, the film stack and bottom physical profile of inter-metal structure is uneven. This explains the reliability response showing dependence on metal line width and bias polarity. We show the E-field distribution is not uniform with the highest E-field density at the bottom corners of metal line. Hence, for a complete inter-metal TDDB reliability qualification, the impacts from test structure design, process variation, and testing methodology need to be considered.

Insights on Inter-metal Reliability Assessment of High Voltage Interconnects

In this work, Gigahertz (GHz) AC signals are stressed at the input terminal of 22 nm FDSOI inverters and the degradation behaviors of transistors in the inverter are found to be different from that under the single device stress. These transistors work under different bias schemes compared to the regular single device measurements, where the AC stress is applied at the gate and DC stress is applied at the drain. To more precisely characterize the transistor reliability in logic circuits, we design the layout to measure the actual degradation of transistors in the inverter directly. The noise margin of the inverter and SRAM cell comprised of this inverter is also studied. The results in this study show that, in a real inverter, the degradation of pMOSFET is overestimated if the BTI result of single device is used.

Degradation Behaviors of 22 nm FDSOI CMOS Inverter Under GHz AC Stress

Short-circuit capability with GaN HEMTs is demonstrated thanks to an integrated Short-Circuit Current Limiter (SCCL) and a commercial gate-driver with DESAT protection. The SCCL is applied to GaN HEMTs to achieve a sufficiently long short-circuit withstanding time (SCWT) while retaining competitive on-state resistance. The SCWT is tuned from 0.3 μs to 3 μs (a remarkable 10x increase) with a relatively small penalty in on-resistance, no leakage increase, no threshold voltage degradation and no reliability degradation. The gate driver has desaturation detection (DESAT) and soft shutdown circuitry to achieve a fast protection response of 800 ns with high noise immunity greater than 100 V/ns. The combination of GaN power devices with SCCL and a commercial gate driver with fastDESAT and high noise immunity allows short-circuit protection and fail-safe operation of GaN power electronics for additional robustness in motor drive applications.

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The Price of Secrecy: How Hiding Internal DRAM Topologies Hurts Rowhammer Defenses

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Study of Avalanche Behavior in 3 kV GaN Vertical P-N Diode Under UIS Stress for Edge-termination Optimization

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