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For plasma process induced damage (PID) qualifications stresses are necessary to detect lifetime reduction risks. JEDEC JEP001 requires HCS, BTS, and TDDB stresses, or a revealing stress for this detection. Due to the large number of devices that should be tested the revealing stress can be preferable. This paper reviews the two main options for the revealing stress for thick oxides, constant gate current (CGC) versus constant gate voltage (CGV) stresses. The results are also intended as input to the discussions in the current JEDEC 14.2 PID standard working group.

IRPS 2022

Revealing stresses for plasma induced damage detection in thick oxides

revealing stress

antenna

plasma damage

technical paper

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The terrestrial Neutron failure rate of SiC JFETs and JFET based Cascode FETs are investigated for the first time.  The contributions of the co-packaged low voltage Si MOSFETs within the Cascode FETs were found to be insignificant in the overall FIT of the high-voltage switches.  Meanwhile, the SiC JFET and resulting Cascode FETs were found to be comparable with the previously reported “Universal” behavior of SiC unipolar devices when analyzed as FIT/cm2 versus applied voltage when normalized to device breakdown voltage.  These results suggest that, due to their superior specific on-resistance (RDS,On x Active Area), SiC JFETs and Cascode FETs will offer lower terrestrial FIT for a given on-resistance. 

Investigation of Terrestrial Neutron Induced Failure Rates in Silicon Carbide JFET Based Cascode FETs

We perform a detailed assessment of the electromigration performance of Co interconnects. Package level EM measurements were performed during &gt;11 months. Our estimate of the EM activation energy is ~1.4 eV which is, within error bar, consistent with earlier reported numbers. Our current exponent estimate suggests that void growth is the dominant contributor to Co EM. Through failure analysis, we associate void growth occurring through grain boundaries and at the barrier/metal interfaces. An activation energy assessment using low frequency noise measurements suggest a stronger contribution from this latter interface. Finally, we make a first estimation of an effective D0Z* for Co of ~1.72×10-10
which is two orders of magnitude lower than for Cu.

Assessment of critical Co electromigration parameters

We characterize the redundancy effect on EM failure time in power grid networks and propose a flow to leverage the benefit of the redundancy effect on EDA tools. Experimental results fit Monte-Carlo simulation based on a parallel model incorporating time-dependent stress loading. Ring oscillator frequency degradation and clock tree time delay are also evaluated on simplified power mesh networks as EM voids occur. A simple and practical EM check algorithm for EDA tools that takes the benefit of the redundancy effect on power grid networks into account is proposed. 

Redundancy Effect on Electromigration Failure Time in Power Grid Networks

For high voltage application, dielectric reliability was investigated on multi-layer inter-level interconnects, focusing on conduction mechanism and geometry effect.  At Vramp (voltage-ramp-to-breakdown) test, Vbd is found to be 4-5% lower with positive bias at bottom metal, which is due to polarity-dependent conduction mechanism.  In addition, metal density affects the lifetime of inter-level TDDB (time-dependent dielectric breakdown) with Poisson area scaling.  Based on our study, we suggest a guideline for additional reliability margin by bias polarity restriction and further layout design optimization.

Polarity Dependence and Metal Density Impact on Multi-Layer Inter-Level TDDB for High Voltage Application

Reliability analysis on Ge Electro-Absorption Modulators suggest that different physical mechanisms are involved in the dark current degradation during electrical stress. An “incubation time” followed by a power-law dependent dark current increase suggests the filling of pre-existing defects and the creation of traps at the Ge/Si and Ge/Ox interface. Even though the dark current degrades during reliability testing, actual failures are not expected to happen at nominal operation conditions and times. Finally, performance evaluation after more than 4000h of electrical stress, reveals no degradation of the electro-optical parameters. 

Degradation mechanisms in Germanium Electro-Absorption Modulators

For the first time, a reliability study on degradation of InGaAs/GaAs nano-ridge p-i-n diodes monolithically integrated on Si by nano-ridge engineering (NRE) is reported. Wafer-level constant current stress in forward bias shows a gradual power law aging of both forward and dark current. Current crowding and Joule heating near the p-contact are responsible for the degradation in forward bias region. Indications of defect formation and Ti diffusion at the metal/GaAs interface are witnessed. The electrical stress-induced leakage current builds up at reverse bias region, pointing to the degradation of crystal quality. A sintering process lowers the p-contact resistance and improves electrical stability. The high aspect-ratio of the trenches leads to effective threading dislocation trapping: no dislocations have been observed to penetrate the active region during the 5000s stress time. This early work sheds light on realizing electrically robust GaAs diodes on Si and reliable monolithic lasers.

Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon

A novel methodology for electromigration (EM) failure assessment in power/ground nets of integrated circuits, which is based on analysis of IR drop degradation, has been enhanced by considering non-uniform temperature distribution in interconnects. Temperature gradient along an interconnect tree can affect void nucleation due to the divergency of atomic flux, as well as due to development of thermal stress. Compact models for resistance increase of voided metal have been developed, using results of FEM simulations of voiding kinetics in via-metal structures. The simulation approach has been validated using measurements of node voltages in a specially designed test power grid. Increase of anode-cathode voltage drop above a threshold value was adopted as a failure criterion determining time-to-failure (TTF) of the grid and mean-time-to-failure (MTTF) was obtained, assuming random distributions of the critical stress and atomic diffusivity. In the studied cases of temperature distributions, a good agreement of simulated and measured TTF distributions has been obtained.

Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation

Understanding the Reliability of Ferroelectric Tunnel Junction Operations using an Advanced Small-Signal Model

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper introduces a modified methodology for conducting OSS in scaled tri-gate devices at accelerated conditions that avoids artifacts associated with punch-through while enabling reliability risk assessment. The methodology is validated for both NMOS &amp; PMOS devices and provides consistent degradation mechanism. Finally, it is shown that on-state gate-oxide TDDB remains the reliability limiter compared to OSS TDDB. 

Method to evaluate off-state breakdown in scaled Tri-gate technologies

The present work aims at investigating how the BGA solder fatigue life in thermal cycling is affected by prior isothermal aging. The Weibull distributions of SAC305 assemblies are considered through failure analysis and microstructural investigations. The main metallurgical effect of isothermal aging observed on solder joints is a strong coalescence of precipitates. The fatigue life was slightly lowered by an extended aging at 100°C while exposure at 150°C proved to increase it. Tin recrystallization and strain-enhanced precipitate coarsening led to intergranular cracking in the solder joints, which was the main failure mode. However, cracking in the PCB laminate was also noticed and mainly present in failed specimens that were previously aged at 150°C. The prior degradation of the board material near its glass transition temperature and the lower stress in the solder joints due to laminate cracking were proposed to explain the unexpected lifetime extension. 

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Revealing stresses for plasma induced damage detection in thick oxides

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Investigation of Terrestrial Neutron Induced Failure Rates in Silicon Carbide JFET Based Cascode FETs

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