United States

The terrestrial Neutron failure rate of SiC JFETs and JFET based Cascode FETs are investigated for the first time.  The contributions of the co-packaged low voltage Si MOSFETs within the Cascode FETs were found to be insignificant in the overall FIT of the high-voltage switches.  Meanwhile, the SiC JFET and resulting Cascode FETs were found to be comparable with the previously reported “Universal” behavior of SiC unipolar devices when analyzed as FIT/cm2 versus applied voltage when normalized to device breakdown voltage.  These results suggest that, due to their superior specific on-resistance (RDS,On x Active Area), SiC JFETs and Cascode FETs will offer lower terrestrial FIT for a given on-resistance. 

IRPS 2022

Investigation of Terrestrial Neutron Induced Failure Rates in Silicon Carbide JFET Based Cascode FETs

terrestrial neutron

jfet

technical paper

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

This paper presents thermal-neutron soft error rates (tnSER) in 7 nm bulk-FinFET technology with applied Cobalt (Co) contact. A thermal-neutron irradiation test at MURR shows tnSER reduction in the 7 nm: the tnSER in the 7 nm (Co-contact) is 0.0012X of the tnSER in 14 nm (Tungsten (W)-contact). Simulation analysis shows that tnSER changed by 0.21X due to the advancement of transistor technology (from 14nm to 7nm) and 0.0057X due to the change in contact-material (from W to Co).




Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology

Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At nominal operating voltage, the 5-nm node has higher SER than the 7‑nm node for all three particle types, with increases of 148%, 168%, and 26%, respectively. The overall SER for the 5-nm node was ~2X greater than that of the 7-nm node, because the reduction in critical charge was higher than that in collected charge. For alpha particle exposures, temperature effects on SER were more prominent for the 5-nm node than both the 7‑nm and 16-nm node. Relative contribution of alpha particle SER increases with scaling, and it accounts for 13% of the overall SER at the 5-nm node. 

Soft Error Characterization for 5-nm Bulk FinFET Technology  in Terrestrial Enviroment

Finfet technology will not be able to keep up with the transistor scaling needs. The development of new transistor architectures, such as nano-wire and nono-sheet transistors are being pursued. Lack of short-channel control results in higher transistor Ioff per unit device width. Combining with more transistors packed in a mm2 Si area and higher Ioff/um, total product standby leakage/cm2 tends to increase with scaling. In addition, the maximum Vdd_stress is getting lower as the design rules are scaled down and the lower-K dielectrics are employed. Higher standby leakage could limit the temperature and voltage that can be used in HTOL testing. HTOL testing strategy in complex SOCs will be presented.
In terms of the reliability of intrinsic core transistors, transistor speed aging and mismatch degradation negatively impact Vmin shift of core logic and memory circuits. For the I/O circuits, lower voltage use at a higher speed demands the use of advanced process nodes, bringing many challenges to circuit design and qualification methodology. A suitable assessment methodology must be implemented to cover reliability weakness of the I/O interfaces. The challenges in reliability qualification testing of ICs will be presented.
In order to meet thermal performance and form factor, IC packaging technology is continuously evolving. These changes can lead to lower solder joint reliability of advanced IC packages. Understanding the mechanical and thermal interaction of new packages with the system board is becoming more important. Both Finite Element Analysis (FEA) and experimental data will be presented to address this critical reliability challenge.


Reliability qualification challenges of SOCs in advanced CMOS process nodes

This paper is demonstrating for the first time a full, industrial-grade, DFT-based approach in 22FDX node combining PVT and Aging compensation, with runtime test solution for hard events detection (TDDB, EMG,..) and Fail Operational mode for compliance with 2018 version of ISO26262 norm

Runtime Test Solution for Adaptive Aging Compensation and Fail Operational Safety mode

In this paper, a new failure model that explains the plasma-induced damage (PID) involving two wells is described. Contrary to common explanation that the larger wells discharge and damage devices in smaller wells, we propose that the damage is caused by an imbalance of the “RC” associated with each “well system”.  The victim gate can reside in either the large or small well.  This RC imbalance model is supported by the results of various test patterns designed in a 0.13um BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer).  New design rules have been developed based on the test pattern results. 

New RC-Imbalance Failure Mechanism of Well Charging Damage and The Implemented Rule

The semiconductor industry has well-established standards for IC reliability requirements, but there is no such standard for board products. IPC-9701A is often referred to when evaluating board level reliability (BLR),  but it doesn’t have clearly defined pass/fail criteria, and it is intended for evaluating BLR of a single component package design, not for complex functional board products such as expensive GPU cards or accelerator cards. This study presents a method of developing cost effective qualification plans for boards by analyzing data of ~45 board temperature cycling runs.  

A Method of Developing Board Qualification Plan

The use-condition lifetime projection from HAST is challenging because self-heated ICs correlate RH and T in a way that is not accounted for by the Peck’s equation. Here: we (i)develop a predictive and self-consistent reliability modeling tool that accounts for the IC self-heating, moisture ingress, and in an integrated way; (ii)demonstrate how the asymmetry between on and off-state heating leads to dramatic suppression of the RH ; and (iii)identify that the corrosion of Cu-Al bond wire occurs in spikes during the on-off transition. Our predictive model suggests an application-aware Generalized Peck’s equation relevant for self-heated ICs under arbitrary operating conditions.  

Reduced Relative Humidity (RH) Enhances the Corrosion-Limited Lifetime of Self-Heated IC: Peck’s equation Generalized

With the steep expansion of the n-type 4H-SiC power metal-oxide-semiconductor field-effect transistor (MOSFET) market space, gate oxide reliability is gaining more and more attention. Although there exist several reports dealing with the bias temperature instability (BTI) under both positive and negative gate biases, gate oxide lifetime evaluations predominantly focus on positive gate bias time-dependent dielectric breakdown (TDDB) stresses for n-channel SiC MOSFETs. In this work we address that gap. From the negative gate bias TDDB data measured at 175 °C and at a gate oxide electric field of about 4 MV/cm, an intrinsic lifetime of 1E8 hours has been predicted, which closely matches with the results obtained from similar devices under positive gate stress. Also, in this work the correlation between failure location in a MOSFET unit cell and the failure signatures during TDDB stress have been established, and an explanation from a device physics standpoint has been provided. The identification of the failure location in the unit cell from in-situ gate leakage data without the need of physical failure analysis can turn out to be key during the early phase of a new process development activity.  

Negative Gate Bias TDDB evaluation of n-Channel SiC Vertical Power MOSFETs

A high rate of early failures in gate oxide is one of the most serious concerns regarding the reliability of silicon carbide metal–oxide–semiconductor field-effect transistors.  Anintensive screening test using high-voltage gate stress is key to reducing this rate.  However, a threshold-voltage (VTH) shift is a frequent side effect, and the degraded chips need to be eliminated. We propose a screening procedure to detect adverse degradation with improved accuracy.  We first analyzed the VTH hysteresis, which deteriorates the measurement accuracy of VTH shifts and found that its wide variation is due to several causes.  We thus investigated multiple consecutive VTH measurements to isolate the hysteretic component from data and confirmed that our procedure is highly useful in detecting the adverse VTH shift.  In particular, it can identify a negative VTH shift hidden by the hysteresis.  This procedure is advantageous for negative-voltage screening in which small gate leakage can alter its VTH.

Accurate screening of defective oxide on SiC using consecutive multiple threshold-voltage measurements

This paper provides a summary of most recent advances and trends in automotive safety, especially related to Automated Driving Systems (ADS). It covers both functional safety, safety of the intended functionality (SOTIF) and their relationships with other areas of dependability such as cybersecurity. It also covers the several standardization activities currently ongoing in safety and Artificial Intelligence. The paper mostly focuses on HW but it also describes the major challenges related to HW-SW interface.

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Investigation of Terrestrial Neutron Induced Failure Rates in Silicon Carbide JFET Based Cascode FETs

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Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology

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