United States

Ultrafast measurements (with 10μs delay) are done to characterize the Negative Bias Temperature Instability (NBTI) and Hot Carrier Degradation (HCD) induced threshold voltage shift (ΔVT) in p-channel Gate All Around Stacked Nano-Sheet (GAA-SNS) Field Effect Transistors (FETs). A model framework is proposed to estimate the measured ΔVT time kinetics during and after NBTI and HCD stress. The BTI Analysis Tool (BAT) framework is calibrated using pure NBTI data (drain bias, VD, at 0V) across gate bias (VG) and temperature (T) and is subsequently used to estimate the underlying NBTI contribution during and after HCD stress under full VG/VD space in the presence of Self-Heating (SH) effect. The pure HCD kinetics is calculated using an empirical model, with VG, VD and T dependence incorporated via a vertical field enhanced dominant energy model.

IRPS 2022

Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress

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CV characteristics of MOS capacitors are classically measured in a few seconds using a capacimeter. Yet it limits the range of useful characterization that can be performed on these devices. For instance BTI reliability characterization is limited by the unavoidable recovery during every measurement step. Likewise, it is almost impossible to characterize properly the hysteresis effect present in some oxides.  Therefore we propose new ultra-fast and powerful CV techniques for MOScap, able to overcome the time limitations of former techniques.


Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

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This paper proposes an accelerator-based neutron beam to evaluate thermal-neutron-induced soft-error rate (tnSER) in semiconductor devices. The thermal-neutron flux is sufficient for the tnSER evaluation in the beam, and the moderator for the beam is compact, and we can perform the tnSER test at many facilities. We have evaluated tnSER in an SRAM with the proposed beam and a nuclear reactor, the tnSER is in good agreement between the tests with the proposed neutron beam and the nuclear reactor. 

Accelerator-Based Thermal-Neutron Beam by Compact and Low-Cost Moderator for Soft-Error Evaluation in Semiconductor Devices

We show our attempt to design space-grade low-power CMOS LSIs enhanced by magnetic tunnel junctions (MTJs). The validity is discussed by using high-energy heavy-ion experiments and macrospin simulations combined with single-event transient noise current modeling. Possible latent damage induced by heavy ions are also explored.

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability

Time and drain bias dependence of HCD under peak ISUB (VG ~ VD/2) stress are modeled. Published n-MOSFET data for different LCH (2.0µm to 37nm), TOX (35nm to 1.85nm), type of junction (HDD, LDD/HDD, SDE/HDD) and stress VD (8V to 1.6V) are analyzed. A compact model is used to model the time kinetics and to explain its difference (i.e., power law or non-power law) in devices having different types of junctions. The dominant energy model is used for VD dependence, and the model parameters are obtained with scaling. The time kinetics and VD dependence are also modeled using TCAD simulations.

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It is well-known that power devices used in high-energy physics and space applications are often subjected to high amounts of radiation. Therefore, it is essential to accurately predict the long-term degradation of these power devices in the presence of radiation. In this paper, we expose LDMOS transistors to various TID of gamma radiation, quantify the dose-dependent generation of interface traps and trapped charges using a novel charge pumping technique; and establish the universality of the degradation kinetics, and illustrate that the model and inferences drawn from the findings in this paper can be applied to other LDMOS devices as well.


Correlated Effects of Radiation and Hot Carrier Degradation on the Performance of LDMOS Transistors

A comprehensive study of electric field (E-field) dependent endurance on Hf-based ferroelectric (FE) fatigue and breakdown mechanism is presented in this study. Under low E-field, reducing E-field worsens FE fatigue and constrains endurance but with no SILC increase as the result of the domain pinning. While under the high E-field stress, endurance is dominated by the field accelerated breakdown due to the increase of oxygen vacancy generation. By utilizing these distinct FE fatigue characteristics under different bias, the recoverable fatigue and prolonged cycle-to-breakdown is observed through a promising high frequency mixed-signal E-field operation.

The Field-dependence Endurance Model and Its Mutual Effect in Hf-based Ferroelectrics

The demand for high-performance computation continues to accelerate. To satisfy this increasing demand, modern server and high-performance computing systems are increasingly deploying nodes with greater heterogeneity and integration. Both trends reduce the cost of computation: heterogeneity by increasing absolute performance, and integration by reducing cost per computation. What has not changed, however, are the stringent reliability, availability, and serviceability (RAS) requirements for nodes used in server and high-performance computing systems. A high level of RAS is required to ensure that data centers deploying nodes can correctly perform computations over their expected lifetime.This paper describes the increased RAS challenges posed by increased heterogeneity and integration. The paper motivates these challenges using data gathered from production systems and presents a case study of the RAS implementation on a highly integrated, heterogeneous node: the AMD EPYC™ and AMD Instinct™ MI250X heterogeneous compute node. Finally, the paper provides a call for standardization to aid in meeting these goals for future data centers.

Reliability, Availability, and Serviceability Challenges for Heterogeneous System Design

In this study, we report an ultra-fast C-V (&gt;4 GHz) measurement methodology for characterizing the high-frequency polarization phenomena in high-k dielectric films. Both HfO2
and Al2O3 films show a significant permittivity decrease under GHz frequencies due to the suppression of ionic polarization. It is the first direct observation of separating ionic and electronic polarization in ultra-thin high-k dielectric films, so far. The phenomena found in this study could be very important for understanding relative physical mechanisms in advanced electron devices, such as ferroelectric and analog devices using high-k dielectric films.

GHz C-V Characterization Methodology and Its Application for Understanding Polarization Behaviors in High-k Dielectric Films

Assessment of transistor degradation in analog circuits during aging effect is challenging due to wide spread of operating points. This paper presents our proposed characterization approaches of full ID-VG
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degradation can be assessed intuitively. Impacts of individual defects on full ID-VG degradation in nanoscale devices are characterized with the proposed approach with high resolution. Thus this paper provides a helpful solution to the characterization of device degradation in analog circuits.

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Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress

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Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

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