United States

Simulations based on first-principle modeling of material structural features determining electrical properties of a CNT memory cell allow to identify a range of operation conditions delivering desirable device characteristics. This approach designates the path for optimization of the CNT memory device structure to meet the performance requirements.   

IRPS 2022

Combining measurements and modeling/simulations analysis to assess carbon nanotube memory cell characteristics

poster

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**PROGRAM AT A GLANCE:**
 

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

We propose a novel method of predicting electron and hole lateral diffusion in a charge trapping layer of 3D TLC NAND by which we can estimate the long-term lateral migration (LM) behavior in a short time. By monitoring the threshold voltage change (△Vth) of the select cell under various bias and temperature conditions, we observe that electron and hole lateral diffusivity matches well with the Poole-Frenkel (PF) model. The lateral diffusivity is extracted by measuring △Vth when the electrons and holes of neighboring cells reach the selected cell. 

Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory

Temperature-accelerated methods are generally used for lifetime evaluations in Flash memories products. However, in this article, an anomalous negative temperature dependence of erase-state threshold voltage (Vt) retention gain in post program/erase (P/E) cycled 3-D NAND Flash memories is reported for the first time, which would lead to a methodological problem of the conventional temperature-accelerated life-test approach. Based on our experiment results, the phenomenon is realized due to the combination of two physical mechanisms. Erase Vt gain at lower temperatures is mainly attributed to silicon nitride (SiN) trapped hole vertical loss via oxide trapped charges created by high P/E cycling stress. At higher bake temperatures, the influence of oxide trapped electron detrapping process is enhanced and Vt gain is therefore reduced. By performing a special experiment, the activation energy of the trapped electron detrapping process is extracted. 

An Abnormal Negative Temperature Dependence of Erase-state Vt Retention Shift in 3-D NAND Flash Memories

New multi-layer ALD HfO2/Al2O3/HfO2
laminate film with a capacitance density 8.3 fF/um2 is evaluated in a MIM capacitor, in 65nm node process, for emerging applications in the automotive space which require higher use voltage and temperature than CMOS logic and DRAM applications. Apart from the typical considerations such as leakage current, capacitance linearity etc. the dielectric relaxation current behavior is also studied. We have performed a thorough reliability study on these films and demonstrate that they meet the stringent requirements for automotive safety applications.

High-k MIM dielectric reliability study in 65nm node

This paper studies the use of 1-selector-1-resistor (1S1R) devices as the cross-point components in a crossbar array for deep neural network (DNN) training. Two training algorithms—minibatch gradient descent (MBGD) and a low-rank approximation to MBGD—are evaluated with compact models of ovonic threshold switching (OTS) selectors considering several reliability issues, and resistive random-access memory (ReRAM), a type of emerging non-volatile memory (NVM) device. We explore various reliability concerns of the OTS selectors including the low on-state conductance, threshold voltage variation, and internal voltage offset, etc. and propose corresponding techniques to overcome the reliability challenges.

Effect of OTS Selector Reliabilities on NVM Crossbar-based Neuromorphic Training

In this paper, the long term data retention characteristics consisting of three main charge loss mechanisms, detrap, trap-assisted tunneling (TAT), and lateral migration (LM), are investigated in charge trap (CT) 3D NAND flash memory. Three mechanisms were completely separated through experiment design, and each activation energy (Ea) was extracted with Arrhenius model well. The detrap mechanism shows the largest Ea, followed by LM and TAT mechanisms. It is interesting that the contribution rate (CR) of each mechanism is related to time-constant (t) in the early part of bake time, and depends on the final charge loss in the latter part of bake time. It is inferred that the retention bottleneck is low program level state at high temperature and is high program level state at low temperature. TAT mechanism dominates the final charge loss regardless of temperature region and program level state. In addition, an effective method is proposed to suppress the LM effect.



Investigation of Retention Characteristics in a Triple-level Charge Trap 3D NAND Flash Memory

This work shows that the complex dynamic-RON characteristics observed for highly scaled HEMT devices results from the similar capture/emission activation energies of the defects present in different epitaxial layers. This work also (i) presents an optimized experimental scheme for a detailed analysis of the different charge-trapping mechanisms in GaN-on-Si HEMTs, (ii) describes the charge-trapping kinetics over a wide range of temperatures using capture/emission time (CET) maps, and (iii) models the defect energy distribution in the AlGaN barrier by analytically deriving the 2D potential profile in the access region and combining it with the results from CET maps.

Interpretation and modelling of dynamic-RON kinetics in GaN-on-Si HEMTs for mmWave applications

Scaled (LG = 0.1 μm) GaN HEMT technology is currently pursued for high-frequency applications (such as 5G), requiring high current/speed and blocking capability. However, traps introduced with intentional Fe doping yield time-dependent breakdown voltage (VBR), seriously affecting reliability. Here, we investigate the role of Fe traps by pulsed I-V characterization performed at different pulse durations (TOFF). A TOFF-dependent VBR is observed on tested devices and is ascribed to the time-dependent occupancy of deep acceptors in the buffer layer. More specifically, the decrease in VBR for short pulses is attributed to the increased leakage due to the reduced ionization of Fe-traps. This interpretation is supported by 2D numerical simulations.

Fe-Traps Influence on Time dependent Breakdown Voltage in 0.1 µm GaN HEMTs for 5G applications

We have investigated and report here for the first time time-dependent dielectric breakdown (TDDB) in 45-nm RFSOI n-channel floating body MOSFETs at cryogenic temperatures. DC constant voltage stress is applied at the gate while the substrate chuck temperature is varied from 300K down to 10K. While t63 decreases with increasing temperature, shape parameter β shows an inverted U-shaped behaviour which is explained using the bandgap model. Three levels of activation energy are seen for high, low and deep low temperatures where the activation energy decreases from high to deep low temperatures. The observed behaviour is further explained using the bandgap as per the percolation theory.

Deep Cryogenic Temperature TDDB in 45-nm PDSOI N-channel FETs for Quantum Computing Applications

Owing to its high power, high efficiency, high gain and high frequency capabilities RF-GaN technology has not only dominated satellite, aerospace and telecom industry but also been tapped as the most promising candidate for 5G technology extension to millimeter wave (MMW) applications. Excellent device performances with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 % have been demonstrated by Wolfspeed's 5G-MMW capable 28 V, 150-nm gate length (V5) GaN on SiC technology. In this work we show the comprehensive DC (both on and off state) and RF reliability assessment and lifetime projection (both DC and RF) of such MMW capable 28 V rated 150-nm gate length process technology (G28V5). The on-state and off-state results coupled with the reliability without hermiticity (RWOH) capability and intrinsic reliability assessment up to 31.5 GHz demonstrate the maturity and reliability of V5 technology as a true candidate for MMW applications.

DC & RF Reliability Assessment of 5G/mmW capable GaN HEMT Process

The sub-THz spectrum between 100GHz and 300GHz is of great interest for achieving next generation 6G cellular network goals of ultra-high data rate, ultra-low latency and high sensing precision. Carrier frequencies &gt;100GHz create significant challenges, including higher losses, lower semiconductor device performance, and a smaller per element physical area that constrains circuit size, integration, power and thermal management. Semiconductor technologies with transistor performance &gt;500GHz are needed for improved efficiency, gain, noise and area at the front end of the 6G phased array radio. Advances in SiGe BiCMOS have the potential to increase silicon transistor performance while leveraging the cost and scale of mature high-volume silicon manufacturing for 6G sub-THz. Compound semiconductor technologies such as InP and GaN have the best front end performance at sub-THz. Advances in heterogeneous and monolithic integration with silicon are needed to address the cost and scale concerns of high frequency InP and GaN.  A comprehensive approach to reliability is essential in order to extract maximum performance without sacrificing reliability.

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Combining measurements and modeling/simulations analysis to assess carbon nanotube memory cell characteristics

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Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory

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