United States

We propose a novel method of predicting electron and hole lateral diffusion in a charge trapping layer of 3D TLC NAND by which we can estimate the long-term lateral migration (LM) behavior in a short time. By monitoring the threshold voltage change (△Vth) of the select cell under various bias and temperature conditions, we observe that electron and hole lateral diffusivity matches well with the Poole-Frenkel (PF) model. The lateral diffusivity is extracted by measuring △Vth when the electrons and holes of neighboring cells reach the selected cell. 

IRPS 2022 Main Conference 

Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Gate oxide Time Dependent Dielectric Breakdown (TDDB) continues to be a major reliability concern for advanced CMOS nodes with increasing quality requirement standard such as for automotive industry. Therefore, significant effort has been made to accurately model gate oxide TDDB. We propose here a modelling approach to account for our recent results showing significant increase of TDDB with frequency.  

Frequency dependant gate oxide TDDB model

Breakdown characteristics of sputtered IGZO films were assessed employing non-identical annealed fixed thickness IGZO metal-insulator-metal (MIM) capacitors. Highest time to breakdown (tBD) in ozone annealed film was attributed to its reduced intrinsic oxygen vacancies (VOI) among remaining samples which was furthermore corroborated by XPS analysis and slope of Weibull distribution (β). For a given sample, β remained weakly insensitive to the field and temperature stresses, though it was dependent on VOI in IGZO film. Furthermore, XPS correlation was made to assess pivotal role of In-O and Ga-O bonds on governing critical breakdown field (EBD) and field acceleration factor (Γ) of IGZO.

Effect of Non-identical Annealing on the Breakdown Characteristics of Sputtered IGZO Films

We report on the gate oxide reliability of n-type LDMOS which is integrated in a 90nm BiCMOS technology and is optimized to offer a robust off-state TDDB reliability performance. In contrast to previous published results, we demonstrate that off-state TDDB lifetimes show very weak dependence on the applied drain bias, Vd, thanks to the carefully optimized NWell drift region that effectively shields the channel from the deleterious high electric fields associated with high Vd operation and significantly reduces the vertical electric field across the gate oxide as shown by TCAD simulation results. TDDB lifetimes are then mainly modulated by the gate voltage and are found to be comparable to the lifetimes obtained under inversion and accumulation modes, hence enabling a reliable operation under high Vdg bias levels. 

Robust Off-State TDDB Reliability of n-LDMOS

We propose a geometric statistical model to describe stress-induced leakage current (SILC) as a function of trap density (Dot). We demonstrate how soft breakdown measured on smaller devices is controlled by a 2 traps percolation path and how its voltage dependence coincides with the 1 to 2 traps transition of SILC measured on larger devices. Finally, assuming the high-k as the breaking layer, we convert the 1-trap leakage current into Dot.

Combining SILC and BD statistics for low-voltage lifetime projection in HK/MG stacks

Gate oxide reliability face a big challenge in high temperature automotive application (auto-grade 0). In this paper, we fully discuss the physical mechanism of oxide trap interaction and point out the oxide reliability weakness. It is found the unexpected TDDB behavior at high temperature, include serious SBD, the relationship of voltage acceleration change, and non-linear temperature effect. In addition, the AC/DC effect found more obvious recovery effect. Finally, for mass production, we also import the confidence level usage to give a reasonable lifetime margin for mass production.

A Realistic Modeling Approach To Explain the Physical Mechanism of TDDB For Automotive Grade-Zero Applications

In this paper, we report middle-of-the-line (MOL) reliability characterization of recessed-diffusion-contact adopted sub-5nm logic technology. The intrinsic MOL reliability including voltage-ramp-to-breakdown (Vramp) and time-dependent-dielectric-breakdown (TDDB) shows a notable improvement. MOL breakdown voltage (Vbd) is also comparable when gate contact is placed next to recessed-diffusion-contact. MOL Vramp related process parameters, such as critical dimension and height, are explained. MOL Vbd as an early diagnosis tool for process maturity, such as contact misalignment and dynamic voltage screening (DVS), on sub-5nm logic technology is addressed.

Middle-of-the-Line Reliability Characterization of Recessed-Diffusion-Contact Adopted sub-5nm Logic Technology

We simulate saturation drain current changes during hot-carrier degradation (HCD) in dynamically-doped (D2) and planar CMOS FETs of a similar architecture. To achieve this, we use our HCD model validated against experimental data over a broad class of transistors. These simulations show that at Vgs ≤ 0.9V (covering the operating regime) D2 FETs have superior reliability, while at Vgs ≥ 1.0V the CMOSFET begins to be more reliable. Under these stress voltages, HCD is governed by the multiple-carrier process of bond dissociation controlled by the carrier concentration (rather than energy), which has different Vgs dependences in D2 and CMOS FETs.

On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors

We present a detailed analysis of Off-state Time Dependent Dielectric Breakdown (TDDB) under non-uniform field performed in MOSFET devices from 28nm FDSOI, 65nm SOI to 130nm nodes. Oxide breakdown in thin gate oxide is characterized under DC stress with different gate-length LG and as function of drain voltage VDS and temperature. We show that the leakage current is a better monitor for TDDB dependence under Off-mode stress whereas a new modeling is proposed. It is found that Weibull slopes β are higher in PFET due large amount of injected hot electrons than in NFET when hot holes are involved.

New Modelling Off-state TDDB for 130nm to 28nm CMOS nodes

Be closer to real product operation, DC TDDB stress convert to AC TDDB could be one choice to wrestle with advanced node shrink limitation. The physical explanation of AC TDDB improvement is successfully interpreted through the analysis of oxide trap generation with HK/IL gate stack in advanced node FinFET technology using SILC spectrum methodology. It is found that AC TDDB improvement is due to more charge de-trap. NMOS show less shallow and deep electron trap generation on HK and PMOS show less hole trap generation on IL during AC waveform transition.

AC TDDB Analysis for HK/IL Gate Stack Breakdown and Frequency-dependent Oxygen Vacancy Trap Generation in Advanced node FinFET Devices by SILC Spectrum Methodology

We have investigated and report here for the first time time-dependent dielectric breakdown (TDDB) in 45-nm RFSOI n-channel floating body MOSFETs at cryogenic temperatures. DC constant voltage stress is applied at the gate while the substrate chuck temperature is varied from 300K down to 10K. While t63 decreases with increasing temperature, shape parameter β shows an inverted U-shaped behaviour which is explained using the bandgap model. Three levels of activation energy are seen for high, low and deep low temperatures where the activation energy decreases from high to deep low temperatures. The observed behaviour is further explained using the bandgap as per the percolation theory.

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Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory

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