United States

We report on the gate oxide reliability of n-type LDMOS which is integrated in a 90nm BiCMOS technology and is optimized to offer a robust off-state TDDB reliability performance. In contrast to previous published results, we demonstrate that off-state TDDB lifetimes show very weak dependence on the applied drain bias, Vd, thanks to the carefully optimized NWell drift region that effectively shields the channel from the deleterious high electric fields associated with high Vd operation and significantly reduces the vertical electric field across the gate oxide as shown by TCAD simulation results. TDDB lifetimes are then mainly modulated by the gate voltage and are found to be comparable to the lifetimes obtained under inversion and accumulation modes, hence enabling a reliable operation under high Vdg bias levels. 

IRPS 2022

Robust Off-State TDDB Reliability of n-LDMOS

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

In this work, we explain the phenomena of ferroelectricity modulation in the ferroelectric (FE) layer due to the residing dielectric (DE) phase. This work also demonstrates the impact of random spatial fluctuation of DE phase for multidomain Metal-Ferro-Insulator-Metal (MFIM) capacitor and Negative Capacitance (NC) FDSOI FET. Using well-calibrated TCAD models, we found: 1) the presence of DE phase causes non-uniformity in the polarization (PFE) and potential (VFE) inside the FE-layer; 2) non-uniformity in the PFEmodulates the average FE capacitance (CFE) due to an increased FE domain interaction; 3) the increase in DE phases decreases the CFE; 4) higher FE thickness (TFE) with higher DE phase exacerbates the CFEvariation, thus, in NC region the PFE becomes direction-dependent; 5) larger DE grain sizes show higher bias directional dependency in the NC region; 6) variation of the coercive field (EC) within the FE layer with DE phase, predominantly increases the bias directional dependency in the  NC region and thereby introduces the higher reliability concerns for NC-FETs. 

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI

Gate oxide Time Dependent Dielectric Breakdown (TDDB) continues to be a major reliability concern for advanced CMOS nodes with increasing quality requirement standard such as for automotive industry. Therefore, significant effort has been made to accurately model gate oxide TDDB. We propose here a modelling approach to account for our recent results showing significant increase of TDDB with frequency.  

Frequency dependant gate oxide TDDB model

Breakdown characteristics of sputtered IGZO films were assessed employing non-identical annealed fixed thickness IGZO metal-insulator-metal (MIM) capacitors. Highest time to breakdown (tBD) in ozone annealed film was attributed to its reduced intrinsic oxygen vacancies (VOI) among remaining samples which was furthermore corroborated by XPS analysis and slope of Weibull distribution (β). For a given sample, β remained weakly insensitive to the field and temperature stresses, though it was dependent on VOI in IGZO film. Furthermore, XPS correlation was made to assess pivotal role of In-O and Ga-O bonds on governing critical breakdown field (EBD) and field acceleration factor (Γ) of IGZO.

Effect of Non-identical Annealing on the Breakdown Characteristics of Sputtered IGZO Films

p-GaN gate HEMTs are attractive transistor structures for power electronics. For reliability and sidewall leakage reasons, it is desirable for the p-GaN layer to extend beyond the edges of the gate metal contact and form an offset. While experimental studies demonstrate wealthy PBTI effects in p-GaN HEMTs, a detailed study of the impact of the p-GaN offset length on device PBTI has yet to be done. Our study reveals a new permanent PBTI degradation mechanism that uniquely takes place in long offset regions that can compromise transistor reliability. We attribute this degradation mechanism to incomplete Mg activation during thermal annealing.

Impact of Gate Offset on PBTI of p-GaN Gate HEMTs

GaN high electron mobility transistors (HEMTs) have limited avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. This work explores the parametric shift and recovery of a commercial Schottky-type, p-gate GaN HEMT under repetitive, overvoltage switching stresses near its dynamic breakdown voltage. In particular, the device recovery under various temperatures is comprehensively studied, which allows the identification of the de-trapping dynamics and dominant trap energy levels for the first time. Devices were stressed in a clamped inductive switching circuit with 1-million surge energy cycles with a voltage overshoot reaching 1300 V. The parametric shifts showed a saturation and were found to be caused by holes generated in impact ionization. The device recovery was found to be accelerated by elevated ambient temperatures, and a hole-trap energy level of 0.52 eV was identified to dominate the parametric shift and recovery. These results suggest the significance of hole dynamics on the overvoltage robustness of p-gate GaN HEMTs near their dynamic breakdown voltage.

Physics of Degradation and Recovery of p-Gate GaN HEMTs under Repetitive Overvoltage Stresses

Oxygen vacancy migration and lead vacancy hole trapping were identified in sputtered lead zirconate titanate thin film by thermally stimulated depolarization current measurement and charge-based deep level transient spectroscopy. The oxygen and lead vacancy were correlated to the first and second wave of resistance degradation, respectively, by the wafer-level process nonuniformity in both electric field polarities, which gives alternatives to process assessment. The concentration of both defects can be controlled by process variations, and the resulting resistance degradation can be modelled using Schottky-limited conduction and two independent defect contributions.  

Defect-controlled Resistance Degradation of Sputtered Lead Zirconate Titanate Thin Films

This paper presents an analysis of power cycling (PC) capabilities of two industry-standard packages with silicon carbide power MOSFET dies: the discrete TO-247 package and a base-plate-less power module with silicone gel encapsulation. PC experiments show a more than an order of magnitude higher number of cycles to failure for the TO-247. The significant spread in the PC lifetime of TO-packaged SiC power MOSFETs by different manufacturers is correlated with die thickness, bond wire diameter, and number of bond wires. A failure analysis and electro-thermo-mechanical simulations point out that shorter PC lifetime in the case of power modules is due to a high stress in solder, while in the case of TO-packages it is ascribed to wire lift-off. The simulations indicate that rather than die thickness, the wire diameter is a critical parameter influencing wire lift-off.  

Power Cycling Reliability of SiC MOSFETs in Discrete and Module Packages

For the first time, we systematically analyzed the cause of gain degradation without physical damage in a discrete III–V device. TCAD simulations verified that excessive stress during componentization was the cause. Medium–level pulse ESD/EOS voltages or TLP currents were zapped at MMIC to reproduce a state without physical damage. We identified soft overstress, reproduced gain drop without physical failure, and isolated the weak position of a  HBT in a discrete device with EMMI.

Progressive Degradation Without Physical Failure During Mounting Due to Soft Overstress in Compound HBT for RF, Mobile, and Automotive Applications

In this paper, we report middle-of-the-line (MOL) reliability characterization of recessed-diffusion-contact adopted sub-5nm logic technology. The intrinsic MOL reliability including voltage-ramp-to-breakdown (Vramp) and time-dependent-dielectric-breakdown (TDDB) shows a notable improvement. MOL breakdown voltage (Vbd) is also comparable when gate contact is placed next to recessed-diffusion-contact. MOL Vramp related process parameters, such as critical dimension and height, are explained. MOL Vbd as an early diagnosis tool for process maturity, such as contact misalignment and dynamic voltage screening (DVS), on sub-5nm logic technology is addressed.

Middle-of-the-Line Reliability Characterization of Recessed-Diffusion-Contact Adopted sub-5nm Logic Technology

We simulate saturation drain current changes during hot-carrier degradation (HCD) in dynamically-doped (D2) and planar CMOS FETs of a similar architecture. To achieve this, we use our HCD model validated against experimental data over a broad class of transistors. These simulations show that at Vgs ≤ 0.9V (covering the operating regime) D2 FETs have superior reliability, while at Vgs ≥ 1.0V the CMOSFET begins to be more reliable. Under these stress voltages, HCD is governed by the multiple-carrier process of bond dissociation controlled by the carrier concentration (rather than energy), which has different Vgs dependences in D2 and CMOS FETs.

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Robust Off-State TDDB Reliability of n-LDMOS

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Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI

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