United States

In this work, we explain the phenomena of ferroelectricity modulation in the ferroelectric (FE) layer due to the residing dielectric (DE) phase. This work also demonstrates the impact of random spatial fluctuation of DE phase for multidomain Metal-Ferro-Insulator-Metal (MFIM) capacitor and Negative Capacitance (NC) FDSOI FET. Using well-calibrated TCAD models, we found: 1) the presence of DE phase causes non-uniformity in the polarization (PFE) and potential (VFE) inside the FE-layer; 2) non-uniformity in the PFEmodulates the average FE capacitance (CFE) due to an increased FE domain interaction; 3) the increase in DE phases decreases the CFE; 4) higher FE thickness (TFE) with higher DE phase exacerbates the CFEvariation, thus, in NC region the PFE becomes direction-dependent; 5) larger DE grain sizes show higher bias directional dependency in the NC region; 6) variation of the coercive field (EC) within the FE layer with DE phase, predominantly increases the bias directional dependency in the  NC region and thereby introduces the higher reliability concerns for NC-FETs. 

IRPS 2022 Main Conference 

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI

poster

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

This work shows an approach to carry out the de-layering, through a series of smart solutions, of the die surface of AlGaN/GaN HEMT with 3 metal levels plus Cu-RDL, after to have performed Fault Localization in the best way – from resolution and wavelengths detection point of view – from the backside of the device without Silicon substrate, that means the final die thickness is ≈ 7µm.
This approach allows advanced physical analysis on AlGaN surface, observing at high resolution and magnification defective points and comparing them with other close areas, improving consistently the global information about the die surface. 

Failure Analysis of AlGaN/GaN Power HEMTs through an innovative sample preparation approach

The single event induced crosstalk of monolithic 3D (M3D) integrated inverter chain is investigated using GEANT4 and TCAD simulations from layout, spacing, length, supply voltage and transistor size. The accurate ionization profiles are initially obtained and modelled in TCAD. Meanwhile, the crosstalk capacitances between interconnect lines or transistors are acquired through 3D simulation. Results show that the crosstalk pulse is closely related to interconnect length and peaks at 50 µm for transistor-level M3D. Vertical alignment of PMOS and NMOS in two inverter chains (gate level) respectively on different tier is the optimal layout to mitigate the single event induced crosstalk pulse (5.9 ps and 130 mV). In addition, increasing thickness of inter-layer dielectric is the best way to eliminate the crosstalk effect nearly without area penalty, which is the intrinsic advantage compared to planar circuits. 

Single event induced crosstalk in monolithic 3D CMOS integrated circuits based on 22 nm FD-SOI

In this work, a detailed analysis of degradation and failure of semi-vertical GaN-on-Si trench MOSFETs is reported. Off-state, semi-on state and on-state conditions were analyzed, to evaluate how the gate and drain bias can impact on the failure voltage. We demonstrate that: a) devices with a bilayer gate insulator (2.5 nm Al2O3 interface dielectric to GaN, + 35 nm SiO2 main dielectric) have a superior performance, compared to single-insulator (35 nm Al2O3) samples; b) in a drain step-stress, the gate voltage (resulting in different operating regimes, off, semi-on or on-state) can significantly impact on the failure voltage of the devices; c) stress at high VGS and/or VDS may induce a significant shift in threshold voltage, which is stronger when the devices are stressed in the on-state. The results – complemented by 2D simulations – provide a description of the factors limiting the breakdown robustness of GaN vertical transistors.

Influence of Drain and Gate Potential on Gate Failure in Semi-Vertical GaN-on-Si Trench MOSFET

p-GaN gate HEMTs are attractive transistor structures for power electronics. For reliability and sidewall leakage reasons, it is desirable for the p-GaN layer to extend beyond the edges of the gate metal contact and form an offset. While experimental studies demonstrate wealthy PBTI effects in p-GaN HEMTs, a detailed study of the impact of the p-GaN offset length on device PBTI has yet to be done. Our study reveals a new permanent PBTI degradation mechanism that uniquely takes place in long offset regions that can compromise transistor reliability. We attribute this degradation mechanism to incomplete Mg activation during thermal annealing.

Impact of Gate Offset on PBTI of p-GaN Gate HEMTs

GaN high electron mobility transistors (HEMTs) have limited avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. This work explores the parametric shift and recovery of a commercial Schottky-type, p-gate GaN HEMT under repetitive, overvoltage switching stresses near its dynamic breakdown voltage. In particular, the device recovery under various temperatures is comprehensively studied, which allows the identification of the de-trapping dynamics and dominant trap energy levels for the first time. Devices were stressed in a clamped inductive switching circuit with 1-million surge energy cycles with a voltage overshoot reaching 1300 V. The parametric shifts showed a saturation and were found to be caused by holes generated in impact ionization. The device recovery was found to be accelerated by elevated ambient temperatures, and a hole-trap energy level of 0.52 eV was identified to dominate the parametric shift and recovery. These results suggest the significance of hole dynamics on the overvoltage robustness of p-gate GaN HEMTs near their dynamic breakdown voltage.

Physics of Degradation and Recovery of p-Gate GaN HEMTs under Repetitive Overvoltage Stresses

In this paper, we propose a novel characterization methodology to study dynamic RON and VTH during a high voltage stress on the drain node of GaN-on-Si E-mode MOSc-HEMTs using a half-bridge configuration circuit and specific gate voltage waveforms. This novel setup enables to study simultaneously RON

and VTH during stress and recovery phases from 10µs to several kiloseconds. At 150°C a high carbon concentration in Carbon-doped GaN layer, reduces ON-Resistance degradation. Temperature dependent measurements show that RON degradation is related to CN acceptor traps in the GaN:C layer. High voltage drain stress induces a combination of VTH
drift and access region related dynamic RON effect.

Novel High Voltage Bias Temperature Instabilities (HV-BTI) setup to monitor RON/VTH drift of GaN-on-Si E-mode MOSc-HEMTs under high drain voltage

The overvoltage and surge energy robustness of GaN power high-electron-mobility transistors (HEMTs) is a key gap recently identified by the JEDEC JC-70.1 committee. This work presents the first study on the parametric shift and recovery of an industrial depletion-mode metal-insulator-semiconductor HEMT (MIS-HEMT) in repetitive overvoltage switching close to its dynamic breakdown voltage. In each switching cycle, a voltage overshoot of up to 90% of dynamic breakdown voltage was applied during the device turn-OFF process. As the repetitive switching prolongs, the device showed shifts in threshold voltage, saturation current, and on-resistance, and these parametric shifts saturated after 1-million cycles. These parametric shifts are believed to be induced by the trapping of the holes generated in the impact ionization. After the repetitive switching, the device exhibited slow recovery in the natural state, at elevated temperatures, or with negative gate biases, due to the difficulty in hole removal. By contrast, applying a positive gate bias or a positive substrate bias can facilitate the hole migration towards the two-dimensional-gas (2DEG) channel for recombination, and therefore, accelerated the device recovery. In particular, a 50-V substrate bias allowed the device to recover in a few minutes. This work shows the good overvoltage robustness of GaN MIS-HEMTs and unveils effective methods for their post-switching recovery, as well as suggests the significance of hole dynamics for the device overvoltage switching close to the dynamic breakdown voltage.

GaN MIS-HEMTs in Repetitive Overvoltage Switching: Parametric Shift and Recovery

Oxygen vacancy migration and lead vacancy hole trapping were identified in sputtered lead zirconate titanate thin film by thermally stimulated depolarization current measurement and charge-based deep level transient spectroscopy. The oxygen and lead vacancy were correlated to the first and second wave of resistance degradation, respectively, by the wafer-level process nonuniformity in both electric field polarities, which gives alternatives to process assessment. The concentration of both defects can be controlled by process variations, and the resulting resistance degradation can be modelled using Schottky-limited conduction and two independent defect contributions.  

Defect-controlled Resistance Degradation of Sputtered Lead Zirconate Titanate Thin Films

This paper presents an analysis of power cycling (PC) capabilities of two industry-standard packages with silicon carbide power MOSFET dies: the discrete TO-247 package and a base-plate-less power module with silicone gel encapsulation. PC experiments show a more than an order of magnitude higher number of cycles to failure for the TO-247. The significant spread in the PC lifetime of TO-packaged SiC power MOSFETs by different manufacturers is correlated with die thickness, bond wire diameter, and number of bond wires. A failure analysis and electro-thermo-mechanical simulations point out that shorter PC lifetime in the case of power modules is due to a high stress in solder, while in the case of TO-packages it is ascribed to wire lift-off. The simulations indicate that rather than die thickness, the wire diameter is a critical parameter influencing wire lift-off.  

Power Cycling Reliability of SiC MOSFETs in Discrete and Module Packages

This paper presents the demonstration of a deep learning-based reconstruction approach for working with 3D X-ray tomography/microscopy data, focusing on improving workflows in microelectronics failure analysis and reliability applications.   Whereas the industry-standard filtered back projection (known as FDK) method of X-ray tomography reconstruction has been used for many years due to its simplicity and robustness, it has constrained the results of 3D X-ray scanning in terms of both image quality and scan speed.  Powered by artificial intelligence technologies, the new deep learning high resolution reconstruction (DLHRR) approach discussed here offers broad improvements across diverse sample types including microelectronics, increases scan speed by a factor of 4X or more, is as easy to use as FDK without requirement for a machine learning expert, and is implemented on a desktop workstation PC.  Results will be shown on IC packages and commercial battery devices.

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Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI

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Failure Analysis of AlGaN/GaN Power HEMTs through an innovative sample preparation approach

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