United States

We characterize the redundancy effect on EM failure time in power grid networks and propose a flow to leverage the benefit of the redundancy effect on EDA tools. Experimental results fit Monte-Carlo simulation based on a parallel model incorporating time-dependent stress loading. Ring oscillator frequency degradation and clock tree time delay are also evaluated on simplified power mesh networks as EM voids occur. A simple and practical EM check algorithm for EDA tools that takes the benefit of the redundancy effect on power grid networks into account is proposed. 

IRPS 2022

Redundancy Effect on Electromigration Failure Time in Power Grid Networks

power grid

redundancy

monte carlo simulation

technical paper

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In this paper, a new failure model that explains the plasma-induced damage (PID) involving two wells is described. Contrary to common explanation that the larger wells discharge and damage devices in smaller wells, we propose that the damage is caused by an imbalance of the “RC” associated with each “well system”.  The victim gate can reside in either the large or small well.  This RC imbalance model is supported by the results of various test patterns designed in a 0.13um BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer).  New design rules have been developed based on the test pattern results. 

New RC-Imbalance Failure Mechanism of Well Charging Damage and The Implemented Rule

The semiconductor industry has well-established standards for IC reliability requirements, but there is no such standard for board products. IPC-9701A is often referred to when evaluating board level reliability (BLR),  but it doesn’t have clearly defined pass/fail criteria, and it is intended for evaluating BLR of a single component package design, not for complex functional board products such as expensive GPU cards or accelerator cards. This study presents a method of developing cost effective qualification plans for boards by analyzing data of ~45 board temperature cycling runs.  

A Method of Developing Board Qualification Plan

The use-condition lifetime projection from HAST is challenging because self-heated ICs correlate RH and T in a way that is not accounted for by the Peck’s equation. Here: we (i)develop a predictive and self-consistent reliability modeling tool that accounts for the IC self-heating, moisture ingress, and in an integrated way; (ii)demonstrate how the asymmetry between on and off-state heating leads to dramatic suppression of the RH ; and (iii)identify that the corrosion of Cu-Al bond wire occurs in spikes during the on-off transition. Our predictive model suggests an application-aware Generalized Peck’s equation relevant for self-heated ICs under arbitrary operating conditions.  

Reduced Relative Humidity (RH) Enhances the Corrosion-Limited Lifetime of Self-Heated IC: Peck’s equation Generalized

With the steep expansion of the n-type 4H-SiC power metal-oxide-semiconductor field-effect transistor (MOSFET) market space, gate oxide reliability is gaining more and more attention. Although there exist several reports dealing with the bias temperature instability (BTI) under both positive and negative gate biases, gate oxide lifetime evaluations predominantly focus on positive gate bias time-dependent dielectric breakdown (TDDB) stresses for n-channel SiC MOSFETs. In this work we address that gap. From the negative gate bias TDDB data measured at 175 °C and at a gate oxide electric field of about 4 MV/cm, an intrinsic lifetime of 1E8 hours has been predicted, which closely matches with the results obtained from similar devices under positive gate stress. Also, in this work the correlation between failure location in a MOSFET unit cell and the failure signatures during TDDB stress have been established, and an explanation from a device physics standpoint has been provided. The identification of the failure location in the unit cell from in-situ gate leakage data without the need of physical failure analysis can turn out to be key during the early phase of a new process development activity.  

Negative Gate Bias TDDB evaluation of n-Channel SiC Vertical Power MOSFETs

A high rate of early failures in gate oxide is one of the most serious concerns regarding the reliability of silicon carbide metal–oxide–semiconductor field-effect transistors.  Anintensive screening test using high-voltage gate stress is key to reducing this rate.  However, a threshold-voltage (VTH) shift is a frequent side effect, and the degraded chips need to be eliminated. We propose a screening procedure to detect adverse degradation with improved accuracy.  We first analyzed the VTH hysteresis, which deteriorates the measurement accuracy of VTH shifts and found that its wide variation is due to several causes.  We thus investigated multiple consecutive VTH measurements to isolate the hysteretic component from data and confirmed that our procedure is highly useful in detecting the adverse VTH shift.  In particular, it can identify a negative VTH shift hidden by the hysteresis.  This procedure is advantageous for negative-voltage screening in which small gate leakage can alter its VTH.

Accurate screening of defective oxide on SiC using consecutive multiple threshold-voltage measurements

The terrestrial Neutron failure rate of SiC JFETs and JFET based Cascode FETs are investigated for the first time.  The contributions of the co-packaged low voltage Si MOSFETs within the Cascode FETs were found to be insignificant in the overall FIT of the high-voltage switches.  Meanwhile, the SiC JFET and resulting Cascode FETs were found to be comparable with the previously reported “Universal” behavior of SiC unipolar devices when analyzed as FIT/cm2 versus applied voltage when normalized to device breakdown voltage.  These results suggest that, due to their superior specific on-resistance (RDS,On x Active Area), SiC JFETs and Cascode FETs will offer lower terrestrial FIT for a given on-resistance. 

Investigation of Terrestrial Neutron Induced Failure Rates in Silicon Carbide JFET Based Cascode FETs

We perform a detailed assessment of the electromigration performance of Co interconnects. Package level EM measurements were performed during &gt;11 months. Our estimate of the EM activation energy is ~1.4 eV which is, within error bar, consistent with earlier reported numbers. Our current exponent estimate suggests that void growth is the dominant contributor to Co EM. Through failure analysis, we associate void growth occurring through grain boundaries and at the barrier/metal interfaces. An activation energy assessment using low frequency noise measurements suggest a stronger contribution from this latter interface. Finally, we make a first estimation of an effective D0Z* for Co of ~1.72×10-10
which is two orders of magnitude lower than for Cu.

Assessment of critical Co electromigration parameters

A novel methodology for electromigration (EM) failure assessment in power/ground nets of integrated circuits, which is based on analysis of IR drop degradation, has been enhanced by considering non-uniform temperature distribution in interconnects. Temperature gradient along an interconnect tree can affect void nucleation due to the divergency of atomic flux, as well as due to development of thermal stress. Compact models for resistance increase of voided metal have been developed, using results of FEM simulations of voiding kinetics in via-metal structures. The simulation approach has been validated using measurements of node voltages in a specially designed test power grid. Increase of anode-cathode voltage drop above a threshold value was adopted as a failure criterion determining time-to-failure (TTF) of the grid and mean-time-to-failure (MTTF) was obtained, assuming random distributions of the critical stress and atomic diffusivity. In the studied cases of temperature distributions, a good agreement of simulated and measured TTF distributions has been obtained.

Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation

Understanding the Reliability of Ferroelectric Tunnel Junction Operations using an Advanced Small-Signal Model

The present work aims at investigating how the BGA solder fatigue life in thermal cycling is affected by prior isothermal aging. The Weibull distributions of SAC305 assemblies are considered through failure analysis and microstructural investigations. The main metallurgical effect of isothermal aging observed on solder joints is a strong coalescence of precipitates. The fatigue life was slightly lowered by an extended aging at 100°C while exposure at 150°C proved to increase it. Tin recrystallization and strain-enhanced precipitate coarsening led to intergranular cracking in the solder joints, which was the main failure mode. However, cracking in the PCB laminate was also noticed and mainly present in failed specimens that were previously aged at 150°C. The prior degradation of the board material near its glass transition temperature and the lower stress in the solder joints due to laminate cracking were proposed to explain the unexpected lifetime extension. 

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Redundancy Effect on Electromigration Failure Time in Power Grid Networks

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