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In this paper, a new failure model that explains the plasma-induced damage (PID) involving two wells is described. Contrary to common explanation that the larger wells discharge and damage devices in smaller wells, we propose that the damage is caused by an imbalance of the “RC” associated with each “well system”.  The victim gate can reside in either the large or small well.  This RC imbalance model is supported by the results of various test patterns designed in a 0.13um BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer).  New design rules have been developed based on the test pattern results. 

IRPS 2022

New RC-Imbalance Failure Mechanism of Well Charging Damage and The Implemented Rule

victim side

aggressor side

cross-domain interface

well charging damage

technical paper

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

n advanced technology, the effect of self-heating (SH) on hot-carrier degradation (HCD) activation energy (Ea) has been studied by temperature correction under DC stress but frequency dependance of HCD under AC condition is discussed thoroughly. In this study, it is experimentally observed that after considering the influence of SH, device lifetime still increases with shorter stress pulse width. Based on these experimental results, a universal HCD model is proposed which could cover both DC and AC stress waveforms with different pulse width (pstress).

Universal Hot Carrier Degradation Model under DC and AC Stress

We report preliminary results on bias temperature instabilities (BTI) on 28FDSOI MOS transistors from 300K to 4K. Common models describe BTI as a temperature-activated effect, which is suppressed at cryogenic temperature. Our measurements show that some BTI remains even at 4K, underlying another degradation mechanism, and we offer insight into the characteristic temperature and time scales. We show that the back-gate voltage can be used to mitigate BTI degradations. An anomalous signal is observed in small PMOS, which can be caused by trapping from the gate.

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K

Periphery pFETs fabricated with the sub-20nm technology are investigated under hot carrier stress conditions when the gate voltage (|Vg|) is lower than the drain voltage (|Vd|). Two types of defects are identified: the donor-like interface trap generation causes the positive charge formation while the electron trapping in oxide traps leads to the negative charge accumulation. The corresponding energy and spatial locations are identified by analyzing the defect-induced mobility degradation and the recovery characteristic. Finally, a defect-based model is proposed for both the threshold voltage shift and the mobility degradation, which allows the prediction of the full IV after aging. This work paves a new avenue to develop accurate reliability model of periphery pFETs, a prerequisite for future device/circuit co-optimization in DRAM peripheral circuits.

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies

The first experimental study of floating-body characteristics for both n- and p-channel devices is demonstrated using the vertical gate-all-around split-gate Flash with channel diameter around 60nm. The maximal Vt shifts are around ~0.38V and 0.32V for n- and p-channel devices, respectively. The retention is ~80usec for n-channel devices, but is extended to nearly 10msec for p-channel devices. 3D TCAD model was established to comprehend the FBC of the vertical split-gate GAA structure. This work suggests the transient charge storage in large GAA diameter. For ordinary Flash memory or LOGIC operations, the aggressive scaled GAA diameter can avoid transient FBC effects.


First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures

This paper presents thermal-neutron soft error rates (tnSER) in 7 nm bulk-FinFET technology with applied Cobalt (Co) contact. A thermal-neutron irradiation test at MURR shows tnSER reduction in the 7 nm: the tnSER in the 7 nm (Co-contact) is 0.0012X of the tnSER in 14 nm (Tungsten (W)-contact). Simulation analysis shows that tnSER changed by 0.21X due to the advancement of transistor technology (from 14nm to 7nm) and 0.0057X due to the change in contact-material (from W to Co).




Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology

Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At nominal operating voltage, the 5-nm node has higher SER than the 7‑nm node for all three particle types, with increases of 148%, 168%, and 26%, respectively. The overall SER for the 5-nm node was ~2X greater than that of the 7-nm node, because the reduction in critical charge was higher than that in collected charge. For alpha particle exposures, temperature effects on SER were more prominent for the 5-nm node than both the 7‑nm and 16-nm node. Relative contribution of alpha particle SER increases with scaling, and it accounts for 13% of the overall SER at the 5-nm node. 

Soft Error Characterization for 5-nm Bulk FinFET Technology in Terrestrial Enviroment

Finfet technology will not be able to keep up with the transistor scaling needs. The development of new transistor architectures, such as nano-wire and nono-sheet transistors are being pursued. Lack of short-channel control results in higher transistor Ioff per unit device width. Combining with more transistors packed in a mm2 Si area and higher Ioff/um, total product standby leakage/cm2 tends to increase with scaling. In addition, the maximum Vdd_stress is getting lower as the design rules are scaled down and the lower-K dielectrics are employed. Higher standby leakage could limit the temperature and voltage that can be used in HTOL testing. HTOL testing strategy in complex SOCs will be presented.
In terms of the reliability of intrinsic core transistors, transistor speed aging and mismatch degradation negatively impact Vmin shift of core logic and memory circuits. For the I/O circuits, lower voltage use at a higher speed demands the use of advanced process nodes, bringing many challenges to circuit design and qualification methodology. A suitable assessment methodology must be implemented to cover reliability weakness of the I/O interfaces. The challenges in reliability qualification testing of ICs will be presented.
In order to meet thermal performance and form factor, IC packaging technology is continuously evolving. These changes can lead to lower solder joint reliability of advanced IC packages. Understanding the mechanical and thermal interaction of new packages with the system board is becoming more important. Both Finite Element Analysis (FEA) and experimental data will be presented to address this critical reliability challenge.


Reliability qualification challenges of SOCs in advanced CMOS process nodes

This paper is demonstrating for the first time a full, industrial-grade, DFT-based approach in 22FDX node combining PVT and Aging compensation, with runtime test solution for hard events detection (TDDB, EMG,..) and Fail Operational mode for compliance with 2018 version of ISO26262 norm

Runtime Test Solution for Adaptive Aging Compensation and Fail Operational Safety mode

This paper provides a summary of most recent advances and trends in automotive safety, especially related to Automated Driving Systems (ADS). It covers both functional safety, safety of the intended functionality (SOTIF) and their relationships with other areas of dependability such as cybersecurity. It also covers the several standardization activities currently ongoing in safety and Artificial Intelligence. The paper mostly focuses on HW but it also describes the major challenges related to HW-SW interface.

Recent advances and trends on automotive safety

In this work we compared AC and DC bias temperature instability (BTI) degradations induced by stressing the channel and Junction-FET regions in 4H polytype n-channel Silicon Carbide (SiC) based power MOSFETs. We observed that the degradation caused by AC BTI stress is dependent on the device technology generation unlike the DC BTI stress degradation, which is found to be independent of technology generation. Also, we found that the AC BTI stress causes more permanent damage to the device due to the creation of interface traps and border traps in contrast to DC BTI where only border traps are responsible for the degradation. 

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New RC-Imbalance Failure Mechanism of Well Charging Damage and The Implemented Rule

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Universal Hot Carrier Degradation Model under DC and AC Stress

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