United States

This work presents a high-voltage-tolerant (HVT) supply clamp for ESD protection, in which the current drive of the clamp during an ESD event is maximized without compromising reliability during normal operation. Similar to prior HVT clamps, ESD current shunting is provided by 3 cascoded NFETs; however, the trigger circuit is improved. The design is implemented in a 45-nm SOI CMOS technology and the clamp devices are sized for a 2-kV HBM protection level. As evidenced by TLP and VFTLP measurements, the new clamp offers 50% reduction of on-resistance and 0.6 V lower turn-on voltage, relative to the prior art.

IRPS 2022

A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology

supply clamp

cmos

technical paper

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Aggressive technology scaling coupled with an insatiable need for high-performance microprocessors has led to a significant increase in power dissipation in integrated circuits. This has, in turn, led to an increase of within-die thermal gradients. In this paper, we present a novel approach of assessing the impact of spatial and temporal hotspots on the chip-package interaction (CPI) reliability of microprocessors using an on-die ring oscillator (ROSC) based heater. The ROSC design enables the generation of temperature hotspots with power densities exceeding 3000 W/cm2, allowing assessment of its impact on CPI reliability. The fast response of the ROSC heater enables high-frequency thermal cycling, which can be used to assess CPI reliability for cycle counts of the order of a few million. This methodology can be used to mimic the thermal cycling behavior of microprocessors under realistic workloads and can be used as a tool to improve confidence in thermo-mechanical reliability.

A Novel Approach for Assessing Impact of Temperature Hot-Spots on Chip-Package Interaction Reliability

It is well known device parameters like mobility can be significantly affected by the stress induced by TSV in 3DIC. For the sake of long-term application, the impact of TSV stress on device reliability also requires attention. This study presents detailed characterization and analysis of TDDB performance of FinFET devices placed in the neighborhood of TSV. It is found the TDDB lifetime of the devices stressed under substrate injection mode could be seriously worsened by neighboring TSV, while that of the devices stressed under gate injection mode only shows moderate degradation. It is proposed the defect generation in high-K layer, which controls the TDDB performance under the former stress mode, may be more sensitive to mechanical stress than that nearby IL/Si interface which dominates under the latter mode. It can be ascribed to considerable charge trappings in HK during stress, which could significantly lower the stiffness of Hf-O and thus reduce the energy required for defect generation under the impact of the stress induced by TSV. It also shows the impact of TSV on TDDB has no considerable orientation dependence. The study suggests careful characterization of the reliability, other than the performance, of the devices nearby TSV with specifically designed test structure, is essential for evaluation of TSV-enabled 3DIC. 

Impact of TSV on TDDB Performance of Neighboring FinFET with HK/IL Gate Stacking

Benefitting from forksheet device co-integration with nanosheets, we evaluate the reliability concerns that come along the use of the SiN-based dielectric wall. This wall could act as a “sponge” for non-equilibrium charges during hot-carrier stress, or absorb charges resulting from the horizontal field between n- and p-type devices. In-depth analysis showed no significant charge trapping phenomena were caused by the presence of the SiN wall. Both BTI and—after accounting for processing imperfections—HCI reliability were found to be comparable. We conclude the SiN dielectric wall does not constitute an additional reliability concern for the novel FSH architecture.

Evaluating Forksheet FET reliability concerns by experimental comparison with co-integrated Nanosheets

Two key mechanisms (i) trapping induced Parasitic Drain Series Resistance (PDSRI) and (ii) interface state generation Nit are both identified within non-conducting hot carrier injection (NCHCI). During NCHCI stress, the drain current degradation due to PDSRI is observed at the first time readout as a sudden shift and is followed by conventional (relatively lower) monotonically increasing shift due to interface state generation. The convolution of these two phenomena, complicates the extraction of their unique model parameters and lifetime extrapolation. Characterization methods to isolate each is demonstrated. Their separate dependencies on gate length, drain voltage, and temperature are 










studied and modeled. Using TCAD simulations, the differences in 
the damage rate and location due to PDSRI and Nit are studied. By 
understanding the E-field distribution, the charge trapping in the 
side wall spacer region is found to be the key contributor to PDSRI 
behavior under NCHCI conditions.

Parasitic Drain Series Resistance Effects on Non-Conducting Hot Carrier Reliability

Significant improvement of channel mobility in SiC MOSFETs with high reliability and deep understanding of bipolar degradation in SiC are presented. By excluding oxidation of SiC while adopting H2 etching prior to oxide formation and interface nitridation, a low interface state density of 6×1010 cm-2eV-1near the conduction band edge was achieved in SiC(0001) MOS structures, which resulted in more than two-fold improvement of channel mobility. A physics-based model for stacking fault expansion upon excess carrier injection is proposed. The critical excess carrier density for stacking fault expansion was estimated to be (4–6)×1014 cm-3 at 300 K. A design guideline of a “recombination-enhancement layer”, which prevents hole injection into the underlying substrate, is described. 

Optical Emission Correlated to Bias Temperature Instability in SiC MOSFETs

We investigate and model the threshold voltage instabilities of 4H-SiC power MOSFETs at room and cryogenic temperatures, based on wide time range (from µs to ks) PBTI analysis. We show that for T &gt; 200 K a stretched (log-like) de-trapping transient dominates the recovery kinetics, while at lower temperatures (down to 80 K) a fast exponential component is also visible. The charge de-trapping process is modeled as a distribution of traps spread over the midgap, that causes the threshold instability. Results indicate: i) one narrow gaussian energy distribution at the interface, visible at low temperature, which explains the exponential transient behavior for T &lt; 200 K; ii) a broader distribution deeper in energy, that is considered to take into account the logarithmic de-trapping kinetics at higher temperatures and the threshold static shift with temperature. The proposed modeling framework can accurately reproduce the experimental results.

Analysis and Modeling of Vth Shift in 4H-SiC MOSFETs  at Room and Cryogenic-Temperature

We investigate the mechanism governing threshold voltage (VTH) hysteresis in packaged SiC MOSFETs. A double-ramp measurement method was employed for this scope, being able to accurately evaluate the time-dependent recovery of the positive VTH shift induced by the sweep-up of the gate voltage. Particularly, we studied the effect of the (i) gate driving voltage (VGH), (ii) recovery time (TOFF) and (iii) temperature (T) on the VTH hysteresis. No appreciable differences were observed among data collected at different VGH, whereas a recovery speed-up was observed at higher T values. Temperature dependent measurement of VTH recovery yielded a 0.3 eV activation energy, that has been associated to SiC/SiO2 interface traps located ~0.3 eV below the SiC conduction band.

Identification of Interface States responsible for VTH Hysteresis in packaged SiC MOSFETs

At the 7-nm bulk FinFET node, latchup effects are seen as limited current increases. In this work, 7-nm node latchup susceptibility is evaluated for terrestrial and space environments as a function of supply voltage, temperature, and particle LET. Holding voltage for latchups is strongly dependent on temperature and was observed to be within 100 mV of nominal supply voltage, therefore latchup can be sustained at elevated supply voltages. Latchup SE cross-section increases with increasing particle LET, increasing supply voltage, and increasing temperature. 

Latchup Vulnerability at the 7-nm FinFET Node

A stress and measurement sequence is presented for the detection of plasma induced damage (PID) instabilities during process reliability monitoring on product wafers of integrated circuit mass production (fWLR Monitoring). The significance of a lifetime estimation from reliability data of antenna test structures is demonstrated with respect to automotive quality requirements in contrary to commonly used approaches in industry. It is shown that a comprehensive approach is necessary starting with appropriate test structures, the PID process qualification and the definition of sophisticated design rules. A short constant current stress as revealing reliability stress for hidden damage fulfills the demands and is discussed in detail including a literature review.

Plasma processing induced charging damage (PID) assessment with appropriate fWLR stress methods ensuring expected MOS reliability and lifetimes for automotive products

This paper presents a new compact model for ESD diodes named Advance SPICE Model for ESD diodes (ASM-ESD). In addition to the current-voltage (I-V) and the capacitance-voltage (C-V) behaviors of the diode under normal operating conditions, ASM-ESD has capabilities to model a plethora of important effects critical for the ESD applications. Model features include the ability to capture the overshoot effects, ambient temperature effects, self-heating effect, post reverse breakdown resistance, parasitic BJT gain, transient behavior of BJT gain and reverse recovery effects in ESD diodes. ASM-ESD model formulations have a physical basis leading to an intuitive extraction flow. Model comparisons with measurements for DC I-V, C-V, and TLP with pulse widths ranging from 200 ns to 1.2 ns are presented. These results demonstrate model accuracy for a full range of ESD event scenarios. 

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A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology

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A Novel Approach for Assessing Impact of Temperature Hot-Spots on Chip-Package Interaction Reliability

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