United States

At the 7-nm bulk FinFET node, latchup effects are seen as limited current increases. In this work, 7-nm node latchup susceptibility is evaluated for terrestrial and space environments as a function of supply voltage, temperature, and particle LET. Holding voltage for latchups is strongly dependent on temperature and was observed to be within 100 mV of nominal supply voltage, therefore latchup can be sustained at elevated supply voltages. Latchup SE cross-section increases with increasing particle LET, increasing supply voltage, and increasing temperature. 

IRPS 2022 Main Conference 

Latchup Vulnerability at the 7-nm FinFET Node

holding voltage

cross-section

single-event latchup

latchup

finfet

technical paper

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Hybrid Bonding (HB) is progressing as the major solution for 3D integrated-circuit with pitch reduction becoming the key. Reliability needs to be studied with HB pitch reduction for possible evaluation of new failure mechanisms and modes. In this paper, we developed a new methodology to study Time-Dependent Dielectric Breakdown (TDDB) at HB level that accounts wafer-to-wafer (W2W) overlay variations. Application of this method to a 1.44 µm-pitch 3D stacked test vehicle demonstrates its accuracy. TDDB at Cu/SiO2 HB interface follows the 1/E model at low electric fields for all studied temperature suggesting that the role of Cu in breakdown is negligible. The acceleration parameter and the activation energy dependence on the electric fields are studied. The cuprous oxide layer which may act as a barrier to Cu diffusion previously highlighted at the Cu/SiO2 HB interface does not exist for Cu/SiN interfaces as evidenced by EELS study. This might explain the difference in the TDDB acceleration models between HB level and BEoL ones. 



New Method to Perform TDDB Tests for Hybrid Bonding Interconnects

Aggressive technology scaling coupled with an insatiable need for high-performance microprocessors has led to a significant increase in power dissipation in integrated circuits. This has, in turn, led to an increase of within-die thermal gradients. In this paper, we present a novel approach of assessing the impact of spatial and temporal hotspots on the chip-package interaction (CPI) reliability of microprocessors using an on-die ring oscillator (ROSC) based heater. The ROSC design enables the generation of temperature hotspots with power densities exceeding 3000 W/cm2, allowing assessment of its impact on CPI reliability. The fast response of the ROSC heater enables high-frequency thermal cycling, which can be used to assess CPI reliability for cycle counts of the order of a few million. This methodology can be used to mimic the thermal cycling behavior of microprocessors under realistic workloads and can be used as a tool to improve confidence in thermo-mechanical reliability.

A Novel Approach for Assessing Impact of Temperature Hot-Spots on Chip-Package Interaction Reliability

It is well known device parameters like mobility can be significantly affected by the stress induced by TSV in 3DIC. For the sake of long-term application, the impact of TSV stress on device reliability also requires attention. This study presents detailed characterization and analysis of TDDB performance of FinFET devices placed in the neighborhood of TSV. It is found the TDDB lifetime of the devices stressed under substrate injection mode could be seriously worsened by neighboring TSV, while that of the devices stressed under gate injection mode only shows moderate degradation. It is proposed the defect generation in high-K layer, which controls the TDDB performance under the former stress mode, may be more sensitive to mechanical stress than that nearby IL/Si interface which dominates under the latter mode. It can be ascribed to considerable charge trappings in HK during stress, which could significantly lower the stiffness of Hf-O and thus reduce the energy required for defect generation under the impact of the stress induced by TSV. It also shows the impact of TSV on TDDB has no considerable orientation dependence. The study suggests careful characterization of the reliability, other than the performance, of the devices nearby TSV with specifically designed test structure, is essential for evaluation of TSV-enabled 3DIC. 

Impact of TSV on TDDB Performance of Neighboring FinFET with HK/IL Gate Stacking

Benefitting from forksheet device co-integration with nanosheets, we evaluate the reliability concerns that come along the use of the SiN-based dielectric wall. This wall could act as a “sponge” for non-equilibrium charges during hot-carrier stress, or absorb charges resulting from the horizontal field between n- and p-type devices. In-depth analysis showed no significant charge trapping phenomena were caused by the presence of the SiN wall. Both BTI and—after accounting for processing imperfections—HCI reliability were found to be comparable. We conclude the SiN dielectric wall does not constitute an additional reliability concern for the novel FSH architecture.

Evaluating Forksheet FET reliability concerns by experimental comparison with co-integrated Nanosheets

Two key mechanisms (i) trapping induced Parasitic Drain Series Resistance (PDSRI) and (ii) interface state generation Nit are both identified within non-conducting hot carrier injection (NCHCI). During NCHCI stress, the drain current degradation due to PDSRI is observed at the first time readout as a sudden shift and is followed by conventional (relatively lower) monotonically increasing shift due to interface state generation. The convolution of these two phenomena, complicates the extraction of their unique model parameters and lifetime extrapolation. Characterization methods to isolate each is demonstrated. Their separate dependencies on gate length, drain voltage, and temperature are 










studied and modeled. Using TCAD simulations, the differences in 
the damage rate and location due to PDSRI and Nit are studied. By 
understanding the E-field distribution, the charge trapping in the 
side wall spacer region is found to be the key contributor to PDSRI 
behavior under NCHCI conditions.

Parasitic Drain Series Resistance Effects on Non-Conducting Hot Carrier Reliability

Significant improvement of channel mobility in SiC MOSFETs with high reliability and deep understanding of bipolar degradation in SiC are presented. By excluding oxidation of SiC while adopting H2 etching prior to oxide formation and interface nitridation, a low interface state density of 6×1010 cm-2eV-1near the conduction band edge was achieved in SiC(0001) MOS structures, which resulted in more than two-fold improvement of channel mobility. A physics-based model for stacking fault expansion upon excess carrier injection is proposed. The critical excess carrier density for stacking fault expansion was estimated to be (4–6)×1014 cm-3 at 300 K. A design guideline of a “recombination-enhancement layer”, which prevents hole injection into the underlying substrate, is described. 

Optical Emission Correlated to Bias Temperature Instability in SiC MOSFETs

We investigate and model the threshold voltage instabilities of 4H-SiC power MOSFETs at room and cryogenic temperatures, based on wide time range (from µs to ks) PBTI analysis. We show that for T &gt; 200 K a stretched (log-like) de-trapping transient dominates the recovery kinetics, while at lower temperatures (down to 80 K) a fast exponential component is also visible. The charge de-trapping process is modeled as a distribution of traps spread over the midgap, that causes the threshold instability. Results indicate: i) one narrow gaussian energy distribution at the interface, visible at low temperature, which explains the exponential transient behavior for T &lt; 200 K; ii) a broader distribution deeper in energy, that is considered to take into account the logarithmic de-trapping kinetics at higher temperatures and the threshold static shift with temperature. The proposed modeling framework can accurately reproduce the experimental results.

Analysis and Modeling of Vth Shift in 4H-SiC MOSFETs at Room and Cryogenic-Temperature

We investigate the mechanism governing threshold voltage (VTH) hysteresis in packaged SiC MOSFETs. A double-ramp measurement method was employed for this scope, being able to accurately evaluate the time-dependent recovery of the positive VTH shift induced by the sweep-up of the gate voltage. Particularly, we studied the effect of the (i) gate driving voltage (VGH), (ii) recovery time (TOFF) and (iii) temperature (T) on the VTH hysteresis. No appreciable differences were observed among data collected at different VGH, whereas a recovery speed-up was observed at higher T values. Temperature dependent measurement of VTH recovery yielded a 0.3 eV activation energy, that has been associated to SiC/SiO2 interface traps located ~0.3 eV below the SiC conduction band.

Identification of Interface States responsible for VTH Hysteresis in packaged SiC MOSFETs

A stress and measurement sequence is presented for the detection of plasma induced damage (PID) instabilities during process reliability monitoring on product wafers of integrated circuit mass production (fWLR Monitoring). The significance of a lifetime estimation from reliability data of antenna test structures is demonstrated with respect to automotive quality requirements in contrary to commonly used approaches in industry. It is shown that a comprehensive approach is necessary starting with appropriate test structures, the PID process qualification and the definition of sophisticated design rules. A short constant current stress as revealing reliability stress for hidden damage fulfills the demands and is discussed in detail including a literature review.

Plasma processing induced charging damage (PID) assessment with appropriate fWLR stress methods ensuring expected MOS reliability and lifetimes for automotive products

This paper presents a new compact model for ESD diodes named Advance SPICE Model for ESD diodes (ASM-ESD). In addition to the current-voltage (I-V) and the capacitance-voltage (C-V) behaviors of the diode under normal operating conditions, ASM-ESD has capabilities to model a plethora of important effects critical for the ESD applications. Model features include the ability to capture the overshoot effects, ambient temperature effects, self-heating effect, post reverse breakdown resistance, parasitic BJT gain, transient behavior of BJT gain and reverse recovery effects in ESD diodes. ASM-ESD model formulations have a physical basis leading to an intuitive extraction flow. Model comparisons with measurements for DC I-V, C-V, and TLP with pulse widths ranging from 200 ns to 1.2 ns are presented. These results demonstrate model accuracy for a full range of ESD event scenarios. 

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New Method to Perform TDDB Tests for Hybrid Bonding Interconnects

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New Method to Perform TDDB Tests for Hybrid Bonding Interconnects

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

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