United States

Hybrid Bonding (HB) is progressing as the major solution for 3D integrated-circuit with pitch reduction becoming the key. Reliability needs to be studied with HB pitch reduction for possible evaluation of new failure mechanisms and modes. In this paper, we developed a new methodology to study Time-Dependent Dielectric Breakdown (TDDB) at HB level that accounts wafer-to-wafer (W2W) overlay variations. Application of this method to a 1.44 µm-pitch 3D stacked test vehicle demonstrates its accuracy. TDDB at Cu/SiO2 HB interface follows the 1/E model at low electric fields for all studied temperature suggesting that the role of Cu in breakdown is negligible. The acceleration parameter and the activation energy dependence on the electric fields are studied. The cuprous oxide layer which may act as a barrier to Cu diffusion previously highlighted at the Cu/SiO2 HB interface does not exist for Cu/SiN interfaces as evidenced by EELS study. This might explain the difference in the TDDB acceleration models between HB level and BEoL ones. 



IRPS 2022

New Method to Perform TDDB Tests for Hybrid Bonding Interconnects

1/e model

cu/sio2 hybrid bonding

tddb

technical paper

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

In SOT-MRAM, the writing path is decoupled from the reading path and therefore considered robust against MgO breakdown in the MTJ. At operation, high current densities flow through the thin metallic SOT layer underneath the MTJ. We find that the SOT track is robust against electromigration, but we observe failure of the MTJ. A thorough chemical analysis indicates the activation of diffusion mechanisms that degrade the free layer and MgO tunnel barrier.

MTJ degradation in SOT-MRAM by self-heating-induced diffusion

Ovonic Threshold Switching Selector faces challenges of VTH stability in intensive applications due to relaxation and the degradation upon endurance cycling. This work investigates the first fire (FF) voltage effects and mechanisms related to the switching characteristics on GeCTe-based selectors. Higher VTH stability and more uniform Ioff-VTH control during endurance cycling were achieved by higher FF design. A power-law model with strong correlation between endurance and pulse-energy was also demonstrated in this study.

Investigation of First Fire Effect on VTH Stability and Endurance in GeCTe Selector

Temperature dependence of charge capture and emission in HfO2 and ferroelectric doped HfO2 are examined over a wide temperature range. Sizeable threshold voltage (Vth) instabilities are observed under cryogenic conditions, contrary to expectation of Arrhenius-based defect freeze-out. The observed data is modelled with the ultra-fast defect levels, located close to the silicon channel. The impact of these traps at room temperature on ferroelectric devices is significant: capture and emission times lie in the range applied for device operation, and can explain the read-after-write delay incorporated in Si-based ferro (FE-)FET operation. 


Modelling ultra-fast threshold voltage instabilities in Hf-based ferroelectrics

Design of reliable and high-performance RF power amplifiers in CMOS technologies is becoming more challenging due to the increasing reliability issues as we approach the scaling limit. To provide insight on hot-carrier injection (HCI) degradation at RF frequencies, this paper presents a comprehensive analysis to study this effect on different PA architectures based on their mission profile with a quasi-static approach. Sensitivity analysis on power amplifier RF performance is also discussed to offer a better understanding on the importance of accurate device and aging behavior modeling. 

Comprehensive Analysis of RF Hot-Carrier Reliability Sensitivity and Design Explorations for 28GHz Power Amplifier Applications

RF reliability of 40-nm PDSOI nFET power amplifier (PA) cell at 26.5GHz is investigated. DC and RF stresses are applied in conducting and non-conducting hot carrier stress mode to study the PA cell RF and DC degradation behaviour. The relationship between DC and large-signal RF performance under various RF stress conditions is investigated using DC and RF metrics. The degradation rate depends on RF power and terminal voltages, where ~8X lower degradation is observed at low VGS. During RF stress, the DC performance degradation rate is higher in the linear operating region than the saturation region. The impact of RF stress is amplified in the presence of DC stress, accelerating the degradation of PA cells. For different VGS under RF stress conditions, the lifetime of the PA cell is calculated and compared.

RF Reliability of CMOS-Based Power Amplifier Cell for 5G mmWave Applications

Power Amplifier (PA) is a key component for embedded RF/mmWave on advanced CMOS technologies on the way to replace the III/V technologies. PA reliability has been a long-standing blocker for those applications. In this paper, a novel methodology is introduced based on an automated waveform analysis tool. Simulation aging results are compared with experimental silicon validation stress for a 28GHz high gain RF Power Amplifier (PA) and confirmed. Waveform analysis tool enables a deeper understanding of both continuous waveform (CW) with constant load and ruggedness test, as well as a new perspective about RF/mmWave circuit aging. 

22FDX™ 5G 28GHz 20dBm Power Amplifier Constant Load and VSWR accelerated aging reliability

RF High Temperature Operating Life (HTOL) of  5G mmWave beamformer chip is evaluated at 28GHz under worst case operating life conditions. Each packaged chip with 8 channel Power Amplifier used for generating omnidirectional beam was evaluated for &gt;= 120hrs at 0.1%CCDF under accelerated Psat RF stress at Tj ~ 85C. Excellent initial RF metrics were observed for all ~32 samples measured. Overall Pout and gain degrades by &lt;0.5dB while DC current degrades &lt;10% meeting the 10yr product life criteria demonstrating excellent RF HTOL processed using GF 45RFSOI technology. Excellent aging model to hardware correlation was also observed showing excellent predictability.

Excellent RF Product HTOL reliability of 5G mmWave beamformer chip fabricated using GF 45RFSOI technologies

The electrical reliability of 1 μm pitch wafer-to-wafer(W2W) Cu/SiCN hybrid bonding interface is evaluated.Breakdown voltage distributions of the W2W hybrid stack wereacquired using the controlled-IV method. Assuming a power lawmodel, extrapolation towards use conditions confirm a lifetimeabove 10 years, with a power law exponent above 10 fortemperatures under 175 C. The conduction mechanism along theCu/SiCN hybrid bonding interface is found to be Poole-Frenkelemission with energy barrier equals 0.95 eV. Mobile copper couldonly be observed at temperatures above 200 C and for fieldsabove 1.5 MV/cm, confirming the good robustness against copperdrift for this bonding interface.

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism

Output power and efficiency of millimeter-wave power amplifiers depend directly on transistor reliability considerations, perhaps more strongly for CMOS-SOI than for any other device technology.  PMOS, in comparison to nMOS, has potential reliability advantages due to 1) higher energy barrier to the gate dielectric from the valence band than from the conduction band; 2) lower impact ionization rate for holes than for electrons at a given electric field; 3) lower channel leakage and parasitic bipolar transistor gain in partially depleted pFETs.  As a result, voltage-handling limits due to hot carrier injection and time-dependent dielectric breakdown are relaxed.  pMOS 28GHz power amplifier ICs which have performance comparable to or better than nMOS are described,  and short-term reliability tests for the amplifiers which show preliminary reliability benefits are presented. 

Reliability of CMOS-SOI power amplifiers for millimeter-wave 5G: the case for pMOS

With HPC devices continue to scale up for higher power and higher power density, thermal dissipation management for IC packages are becoming an important issue. This paper presents the thermal solution evolution at package level and system level, that drives towards more advanced package TIM1 solution and liquid or immersion cooling solution. Thermal-aware device floorplan, package thermal solution and advanced system cooling solution are critical to enable HPC application.

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New Method to Perform TDDB Tests for Hybrid Bonding Interconnects

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MTJ degradation in SOT-MRAM by self-heating-induced diffusion

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