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Ovonic Threshold Switching Selector faces challenges of VTH stability in intensive applications due to relaxation and the degradation upon endurance cycling. This work investigates the first fire (FF) voltage effects and mechanisms related to the switching characteristics on GeCTe-based selectors. Higher VTH stability and more uniform Ioff-VTH control during endurance cycling were achieved by higher FF design. A power-law model with strong correlation between endurance and pulse-energy was also demonstrated in this study.

IRPS 2022

Investigation of First Fire Effect on VTH Stability and Endurance in GeCTe Selector

acceleration.

cycling degradation

relaxation

gecte

ovonic threshold switching selector

endurance

stability

technical paper

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In-memory computing (IMC) with memory arrays allows reducing the time and energy consumption for matrix vector multiplication (MVM) for artificial neural networks (ANN) inference. However, the IMC accuracy is affected by nonidealities, such as program/read variations of device conductance and the parasitic voltage (IR) drop along the wires, whose impact quickly increases when increasing the array size. This work presents new IMC circuit architectures for mitigating both variations and IR drop at the same time. The  new schemes allow for improving the accuracy of an ANN from 72.7% to 94.9%, compared to a software accuracy of 96.9%, at the expense of an increase of the memory array area.

Mitigating read-program variation and IR drop by circuit architecture in RRAM-based neural network accelerators

Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.

Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators

We investigate the impact of charge-trapping on ferroelectric (FE) switching and its influence on memory window (MW) and retention of FeFET. Fabricated FinFETs with ferroelectric gate stack were used to study defects properties (within HZO), trapping/FE-switching interplay, and dynamics. Starting from the electronic-assisted nucleation of FE domains, we investigated the interface charging and degradation, as well as their impact on the polarization compensation, MW and stabilization of the retention. Finally, a balance between those competing processes was analyzed and a retention model of FeFET (capturing behavior over device’s lifetime) was developed 

Electron-assisted switching in FeFETs: MW dynamics – retention - trapping mechanisms and correlation

In SOT-MRAM, the writing path is decoupled from the reading path and therefore considered robust against MgO breakdown in the MTJ. At operation, high current densities flow through the thin metallic SOT layer underneath the MTJ. We find that the SOT track is robust against electromigration, but we observe failure of the MTJ. A thorough chemical analysis indicates the activation of diffusion mechanisms that degrade the free layer and MgO tunnel barrier.

MTJ degradation in SOT-MRAM by self-heating-induced diffusion

This work presents the influence of SiC epitaxial wafer quality on yield of SiC-DMOSFETs. Various wafer quality indicators were estimated by an integrated wafer quality evaluation system. SiC-DMOSFETs were fabricated on six 100 mm 4H-SiC epitaxial wafers. We show that the yield of SiC-DMOSFETs is related to threading screw dislocation density, defect density and bunched-steps length density evaluated by wafer inspection apparatuses.

Influence of SiC epitaxial wafer quality on yield of 1.2kV SiC-DMOSFETs

Power device characteristics are affected by X-rays used during the inspection of power modules. In this study, the effects of materials and structures of power MOSFETs on the overall degradation were analyzed by irradiating Si MOSFETs and SiC MOSFETs with X-rays using a commercial inspection system. In addition, the effectiveness of thermal and gate voltage annealing was investigated for the irradiated devices. The experimental results confirmed the high radiation tolerance of SiC MOSFETs. In addition, the irradiated devices exhibited difficulty in recovering the shifted threshold voltage without compromising the reliability of the device, indicating that the effects of degradation persisted for a long time.

Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Its Recovery

Forty nine silicon carbide 150 mm wafers from three commercial vendors to be used for fabricating MOSFETs were examined by UVPL imaging to count their concentration of basal plane dislocations, inclusions, micropipes and trapezoids. The wafers were from three vendors, and wafers with 10 um, 30 um and 60 um epitaxial layers were evaluated. The wafers with 10 um and 30 um epilayers were virtually free of BPDs, while BPD concentrations of the wafers with 60 um were too high for commercial use.  Concentrations of inclusions, micropipes and trapezoids were also evaluated. Most of the wafers had acceptable levels of these defects, but device yield would be improved by more consistently having low concentrations.

Defects in 4H-SiC Epilayers That Affect Device Yield and Reliability

The electron trapping in gate oxides of m-plane SiC-MOS capacitors were studied by electron injection. The trapped electron densities calculated using the flat-band voltage shift were analyzed. There are possibly three types of electron traps with different capture cross sections. The oxide grown by LPCVD has slightly lower electron trap density than the oxides by thermal oxidation or TEOS-PECVD. The obtained trapped electron densities were found to be one order of magnitude higher than that of Si-MOS and there may be large room for improvement of the electron trap in the gate oxide of SiC-MOSFET for better VT reliability.

Characterization of Electron Traps in Gate Oxide of SiC MOS Capacitors

Several designs of 1.2kV-rated 4H-SiC PiN diodes and Junction Barrier Schottky (JBS) diodes have been successfully fabricated with various P+ implantation conditions resulting in different junction profiles. P+ regions were implanted at both room temperature and elevated temperature in order to monitor the generation of Basal Plane Dislocations (BPDs) and study their impact on device long term reliability. It was found that, when the dose in the deeper portion of the junction (implemented by high energy) is well suppressed, static and long-term reliability performances of room temperature implanted devices can be maintained similar to those of high temperature implanted devices.

Static Performance and Reliability of 4H-SiC Diodes with P+ Regions Formed by Various Profiles and Temperatures

The advent of Artificial Intelligence (AI) and big data era brought an unprecedented (and ever growing) need for fast and energy efficient computation that cannot be obtained with the classical von Neumann computing architecture. This paved the way to new technologies that try to mimic the human brain to leverage its energy efficient and distributed computing. Non-volatile memory technologies seem to be the ideal solution for the hardware implementation of artificial neurons and synapses of Neural Network (NN) architectures and have been extensively investigated in the last years. However, they often suffer from limited linearity and symmetry, poor retention, and high variability, thus requiring significant advancements for their mass adoption in NNs. One of the cornerstones on which the required efforts must be based is certainly represented by device simulations, which can be effectively used to achieve a full understanding of the physics governing the device, which in turn is a pre-requisite for their design, optimization and successful exploitation in neuromorphic applications. In this scenario, we focus on Transition Metal Oxide (TMO)-based RRAM, Ferroelectric Tunnel Junctions (FTJ) and 3D-NAND Charge Trap devices and use simulations to address key issues related to neuromorphic operation (linearity and asymmetry) and reliability (variability and retention).  

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Investigation of First Fire Effect on VTH Stability and Endurance in GeCTe Selector

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Mitigating read-program variation and IR drop by circuit architecture in RRAM-based neural network accelerators

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