United States

We report a record SC robustness of a novel vertical GaN Fin-JFET. This Fin-JFET has an 800 V avalanche breakdown voltage (BVAVA). The tSC is measured to be 30.5 us  at 400 V and 11.6 us  at BVAVA.  As far as we know, this is the first report of a power transistor with robust short-circuit ruggedness at BVAVA. The underlying mechanism is the unique avalanche-through-fin which is verified by TCAD simulation and UIS test. These results alleviate the concern of SC robustness of GaN devices and demonstrate the potential of vertical GaN Fin JFETs in future power applications.

IRPS 2022

Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage

power device robustness

vertical gan fin-jfet

short circuit

avalanche

technical paper

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

In this work, we develop an inherently self-consistent methodology to resolve the long-standing challenges of variability-induced TDDB degradation in MOL/BEOL/MIMCAP applications. A grand scheme of modelling methodology is outlined to accurately extract degradation parameters (distribution scale and shape factors) in matching experimental data while maintaining the methodology rigour.   We identify not only the degradation parameters affecting TDDB performance but also a variety of variability distributions as well as their bimodality in superposition or competition as additional sources of variability.  We show excellent agreement with large sets of experimental data. The methodology can be readily used for accurate reliability projection. 

A Flexible and Inherently Self-Consistent Methodology for MOL/BEOL/MIMCAP TDDB Applications with Excessive Variability-Induced Degradation

The current understanding of key reliability phenomena such as leakage and Random Telegraph Noise (RTN) is still incomplete. Models exist that explain simple cases (2-level RTN), yet experimental reports showed the occurrence of complex cases (e.g., coupled RTN, anomalous and temporary RTN) that deserve deeper investigation. In this paper, we focus on the often overlooked role of trapped charge in the electrostatic coupling among defects, entailing a multi-body problem, and on the related effects on leakage and RTN. The electric field in the dielectric is found to be usually dominated by the trapped charge rather than by the applied voltage, defying common beliefs and elegantly explaining some of the aforesaid complex scenarios. We demonstrate that such defects interactions are responsible for a strong modulation of the capture and emission time constants over time. Moreover, we highlight how defects capture/emission source/destination can change with the local field and therefore with the applied voltage, which gives rise to non-monotonic trends in tc/te vs. applied voltage plot. This last point reveals that the classical formula adopted for the estimation of the defects vertical position within the dielectric is oversimplified and may lead to significant errors. The results of this study advance the understanding of leakage and RTN, and can be useful for the design of applications such as low-power Physical Unclonable Functions and True Random Number Generators. 

The Relevance of Trapped Charge for Leakage and Random Telegraph Noise Phenomena

This paper reports BTI trends in high-voltage transistors for memory periphery devices with SiO2/Poly and High-K/Metal gate stacks. For PBTI, we present an extension to the typical power law kinetics that is related to the creation of interface states due to hot electrons transported through the gate oxide. This extension enables a good fit of accelerated test data and, thereby, lifetime extrapolation. We then explore EOT and gate stack trends in PBTI. For NBTI, we report gate stack, EOT, and thermal budget trends.

BTI of High-Voltage Logic-for-Memory Devices

The assessment of the reliability of MEMS under high-g shock has been challenging and primarily relied on experiments. In this paper, we proposed an analytical model that more accurately described the transient response of MEMS under high-g shock than the currently adopted half-sine description of shock load in the industrial testing standards. Furthermore, we proposed a reliability index to assess the threshold of the shock amplitude that MEMS structures could survive with the vibrating and fading features of the shock considered. The numerical results based on the shock response spectrum (SRS) analysis have shown excellent accuracy of our proposed model of ours. The index revealed that the reliability of MEMS structure could be significantly lower under a shock of short duration than it under quasi-static acceleration impulse.

An Analytical Model of Transient Response of MEMS under High-G shock for Reliability Assessment

MEMS designed for high-g shock environments tend to sacrifice their structural performance for reliability concerns. The size and shape of the micro-beam are critical for both the performance and reliability of MEMS. This paper proposes an optimization method that can exploit the structural performance of MEMS beams under mechanical overload. First, we proposed a reliability model to quantify the fracture probability of MEMS beam under shock. Secondly, a performance optimization problem was established based on the variable cross-section beam structure. Finally, the optimal shape of four typical types of MEMS beam was obtained numerically. Without sacrificing their reliability under high-g shock, the driving voltage and the structural sensitivity of the beam of optimal shape were improved by 13-49% and 32-79%, which is a practical optimization design by not changing the manufacturing process drastically. 

The Optimal Shape of MEMS Beam Under High-G Shock Based on a Probabilistic Fracture Model

Negative bias temperature instability (NBTI) is a critical concern for CMOS reliability and ultra-fast test system for ID–VG characterization at the µs time scale is usually needed due to device relaxation. Poly heater structure provides in situ temperature changes to allow different temperatures for stress and measurement in NBTI characterization to reduce recovery in measurement. In this paper NBTI characterization for 5V PMOS devices in a 0.18µm smart power technology utilizing poly heater in a standard test system was investigated with good agreement to test results from fast measurement system.

NBTI Characterization with in Situ Poly Heater

Antenna rules relating to well charging is becoming an important aspect to consider in the design rule checks apart from the conventional antenna to gate ratio design rules. In this paper, we provided a better understanding of the well charging phenomena with different layout configurations and introduced a new power law correlation with well exponent based on characterized data. A comparison of well charging design solutions is presented and validated on circuit-like test structures. 

A Deeper Understanding of Well Charging Reliability with Circuit Relevant Test Structures

We propose an electrical detection method for peripheral circuit (PERI) ‘open’ random defects. This brand new screening methodology detects only PERI defects by independently controlling the supply voltage (VDD) of each circuitry array at low temperature. The proposed method is confirmed based on experimental, simulation, and physical analysis results. Compared with conventional function test items, our proposed method shows &gt;50% error reduction.

Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory

The block size of flash memory chips has increased significantly with the introduction of 3D NAND technology, causing “big-block” management issues in storage systems. In this paper, we characterize endurance of individual pages in a block and show that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. This variation in endurance among pages can cause severe underutilization of big memory blocks. We find that erase threshold voltage () variation between the layers is the root cause for the observed endurance variation. 

Layer-to-Layer Endurance Variation of 3D NAND

Field-effect transistors (FETs) based on two-dimensional (2D) materials hold the promise to allow for ultimately scaled channel thicknesses of single monolayers. Due to their ultimately small thicknesses, the gate control is enhanced while sizable mobilities in the 2D semiconductors are maintained. Thus, in recent years considerable research efforts have focused on 2D FETs and explored various 2D semiconductors and their properties. However, the key challenge of finding suitable gate insulators for 2D FETs has yet received little attention. In this paper, criteria are formulated for identifying suitable gate insulators for reliable 2D FETs. The criteria are grouped into three main categories, these are scaling requirements, reduction of insulator-related charge traps, and technological requirements for the insulator deposition. In addition, possible candidates for gate insulators for 2D FETs are evaluated with respect to the formulated criteria, and important research questions for future investigations are identified.

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Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage

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A Flexible and Inherently Self-Consistent Methodology for MOL/BEOL/MIMCAP TDDB Applications with Excessive Variability-Induced Degradation

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