United States

In this work, we develop an inherently self-consistent methodology to resolve the long-standing challenges of variability-induced TDDB degradation in MOL/BEOL/MIMCAP applications. A grand scheme of modelling methodology is outlined to accurately extract degradation parameters (distribution scale and shape factors) in matching experimental data while maintaining the methodology rigour.   We identify not only the degradation parameters affecting TDDB performance but also a variety of variability distributions as well as their bimodality in superposition or competition as additional sources of variability.  We show excellent agreement with large sets of experimental data. The methodology can be readily used for accurate reliability projection. 

IRPS 2022

A Flexible and Inherently Self-Consistent Methodology for MOL/BEOL/MIMCAP TDDB Applications with Excessive Variability-Induced Degradation

tddb

variability

degradation

technical paper

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/6b7a695cee2a4e6d07c0594938f00e41.png)](https://drive.google.com/file/d/1_V_fHL72jJWTmq-pUe-JJAR97y3dN5RX/view?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/924447c4755e4e804db480b0504f6c13.png)](https://drive.google.com/drive/folders/1Mxu8R6jiCM_F1m_4pFdqgVKDfYaoTbtn?usp=sharing)
[![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)

 


![](https://assets.underline.io/uploads/markdown_image/1/image/e1ce7df3286ab3a750966a5bf555716e.png)
 


**PROGRAM AT A GLANCE:**
 

![](https://assets.underline.io/uploads/markdown_image/1/image/fd55e96d31b53ac223d4e9b8d0186848.png)

 

**2022 IEEE International Reliability Physics Symposium has gone mobile!**

![](https://assets.underline.io/uploads/markdown_image/1/image/07a1cc9ee775657110a89eddbcc41388.jpg)

 


![](https://assets.underline.io/uploads/markdown_image/1/image/7a5e45b43771adf5ae4d3f97c1861ac1.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/a0cab03a0ec30cc71c71b5efec2ba603.png)](https://www.amd.com/en)[![](https://assets.underline.io/uploads/markdown_image/1/image/2921931b8aa0a090d96fd463670a0305.png)](https://www.cisco.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/d0cd3844560c9bdf8d4303b36d82dc69.png)](https://amazon.jobs/en/teams/lab126/)

![](https://assets.underline.io/uploads/markdown_image/1/image/c849d66095021f867725ff54b2c1f53e.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/8e648631fe7093b9613454de264d6745.png)](https://www.intel.com/content/www/us/en/homepage.html)[![](https://assets.underline.io/uploads/markdown_image/1/image/76970c33d96c19445badc60c21d890e8.png)](https://www.kioxia.com/en-emea/top.html)[![](https://assets.underline.io/uploads/markdown_image/1/image/546ecacb92116a8373a0cb2b3462dc1e.png)](https://about.google/)[![](https://assets.underline.io/uploads/markdown_image/1/image/91dca9e7aff5399ce0ea709d196c4f6a.png)](https://www.ibm.com/hr-en)[![](https://assets.underline.io/uploads/markdown_image/1/image/d1a1c95a5b0b551edea10f686f959c0d.png)](https://www.qualcomm.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/fa628a3cef7a5300e4ab59da0e0552fa.png)](https://www.samsung.com/hr/smartphones/galaxy-s22-ultra/?page=home)[![](https://assets.underline.io/uploads/markdown_image/1/image/948a0108c6b1b84e336b6f39bbc57fcf.png)](https://www.micron.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/74e631e654862d71a16d009817467e5c.png)](https://www.nvidia.com/en-eu/geforce/)[![](https://assets.underline.io/uploads/markdown_image/1/image/224a109509478bb0c4d361401ba65fae.png)](https://www.tsmc.com/english)[![](https://assets.underline.io/uploads/markdown_image/1/image/d70304be54ef831492c3cb99d8c1f3c7.png)](https://www.tel.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/7e60586f1c46e0157f2f452d4005fb54.png)](https://gf.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/e1c9bbe8892bbd4d89b81de064f31dfa.png)](https://www.appliedmaterials.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/dc19add30e3105172bdc93580e944dee.png)](https://www.ti.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/8e81ebc466ddd94f3fde7f3cdebb86c0.png)](https://www.skhynix.com/)[![](https://assets.underline.io/uploads/markdown_image/1/image/ccfa43258b058874e38e5903f79e63bc.png)](https://www.st.com/content/st_com/en.html)

 
![](https://assets.underline.io/uploads/markdown_image/1/image/e4c5690a7016a468518eeab6ed0f7e56.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/c33da95f78e91c05d51b787f02a1af01.png)](https://www.infineon.com/)
![](https://assets.underline.io/uploads/markdown_image/1/image/e708450912afd1718c5af9e9dfd70d3f.png)
[![](https://assets.underline.io/uploads/markdown_image/1/image/ffd1b2531ec1531672693a786e5a1b37.png)](https://eds.ieee.org/)[![](https://assets.underline.io/uploads/markdown_image/1/image/0a58c969093f21f088af904b1cb4e112.png)](https://rs.ieee.org/)

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

This paper will discuss how deep data analytics based on Universal Chip Telemetry™ (UCT) offers a new approach to lifecycle health and performance monitoring in advanced electronics. By combining on-chip monitoring with machine learning inference in the cloud and edge, production quality is improved through advanced latent defect detection, while lifetime reliability is increased through degradation monitoring and predictive fault detection.

Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics

Contacts stability versus thermal budget is a major concern in 3D sequential integration. We experimentally investigate the thermal stability of n-type contacts on Si and p-type contacts on SiGe in terms of specific contact resistivity (ρc). An improved ρcn performance featuring lower magnitude and better thermal stability has been demonstrated for Ti silicide contacts on n+-Si with Ge pre-amorphization implantation (PAI). For p-type contacts, it is found that Ni has lost its high work function advantage on p++-SiGe and Ti germanosilicide contacts show ρcp outperformance. CMOS contact scheme based on single Ti instead of dual Ti and Ni has hence been evidenced to be more suitable for 3D sequential integration.

Investigation on Contacts Thermal Stability for 3D Sequential Integration

Silicon oxynitride (SiON) is widely applied as ultra-thin gate oxide for LNA, with its better resistance to high electric field stress and higher dielectric constant than conventional SiO2. However, the gate leakage still inevitably increases to a non-negligible level as gate oxide been thinned down till &lt;15A.  In this paper, rapid thermal process (RTP) was employed to fabricate a series of SiON gate oxide film. It was found that pre-Nitridation O2 treatment at lower temperature effectively optimize the N-dose profile in SiON and suppresses the gate leakage without significant impact on LNA DC/RF performance. .

Pre-O2 treatment for LNA gate oxide leakage improvement

The assessment of the reliability of MEMS under high-g shock has been challenging and primarily relied on experiments. In this paper, we proposed an analytical model that more accurately described the transient response of MEMS under high-g shock than the currently adopted half-sine description of shock load in the industrial testing standards. Furthermore, we proposed a reliability index to assess the threshold of the shock amplitude that MEMS structures could survive with the vibrating and fading features of the shock considered. The numerical results based on the shock response spectrum (SRS) analysis have shown excellent accuracy of our proposed model of ours. The index revealed that the reliability of MEMS structure could be significantly lower under a shock of short duration than it under quasi-static acceleration impulse.

An Analytical Model of Transient Response of MEMS under High-G shock for Reliability Assessment

MEMS designed for high-g shock environments tend to sacrifice their structural performance for reliability concerns. The size and shape of the micro-beam are critical for both the performance and reliability of MEMS. This paper proposes an optimization method that can exploit the structural performance of MEMS beams under mechanical overload. First, we proposed a reliability model to quantify the fracture probability of MEMS beam under shock. Secondly, a performance optimization problem was established based on the variable cross-section beam structure. Finally, the optimal shape of four typical types of MEMS beam was obtained numerically. Without sacrificing their reliability under high-g shock, the driving voltage and the structural sensitivity of the beam of optimal shape were improved by 13-49% and 32-79%, which is a practical optimization design by not changing the manufacturing process drastically. 

The Optimal Shape of MEMS Beam Under High-G Shock Based on a Probabilistic Fracture Model

We propose an electrical detection method for peripheral circuit (PERI) ‘open’ random defects. This brand new screening methodology detects only PERI defects by independently controlling the supply voltage (VDD) of each circuitry array at low temperature. The proposed method is confirmed based on experimental, simulation, and physical analysis results. Compared with conventional function test items, our proposed method shows &gt;50% error reduction.

Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory

On-chip degradation monitoring enables reliable recycling of chips in the context of circular economy by assessing their degradation and thereby inferring their remaining lifetime. Implementations of such monitors have already been presented typically relying on ring-oscillator-based circuits to evaluate degradation undergone by ICs. However, these approaches are not able to distinguish between the physical degradation and the time since fabrication and they can be tampered with high temperature annealing. In this work we present a new concept of degradation monitor circuit, which can obtain the age of the chip and detect if the chip has undergone tampering through high-temperature annealing.

A Ring-Oscillator-based Degradation Monitor Concept with Tamper Detection Capability

For the design of reliable ICs the application of accurate transistor aging models is indispensable. However, especially for modern deeply-scaled technologies modeling NBTI induced aging poses significant challenges as transistors can not be characterized individually but need to be described as a statistical ensemble. We make use of a dedicated array structure enabling the collection of a large data-set at reasonable experimental time. Note that by using an extensive data-set the statistical confidence can be maximized. We present a modeling approach based on physical considerations to describe the aging of SRAM-sized transistors under consideration of statistical effects. Our approach applies a modified defect-centric model under consideration of RTN to describe the time-dependent Vth distribution. Furthermore, we introduce a simple method to extract parameters describing the distribution. Additionally, we show that our approach provides great flexibility regarding stress conditions as well as scalability to different transistor dimensions, which makes it ideal for applications such as circuit simulation.

Efficient Evaluation of the Time-Dependent Threshold Voltage Distribution Due to NBTI Stress Using Transistor Arrays

The block size of flash memory chips has increased significantly with the introduction of 3D NAND technology, causing “big-block” management issues in storage systems. In this paper, we characterize endurance of individual pages in a block and show that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. This variation in endurance among pages can cause severe underutilization of big memory blocks. We find that erase threshold voltage () variation between the layers is the root cause for the observed endurance variation. 

Layer-to-Layer Endurance Variation of 3D NAND

Field-effect transistors (FETs) based on two-dimensional (2D) materials hold the promise to allow for ultimately scaled channel thicknesses of single monolayers. Due to their ultimately small thicknesses, the gate control is enhanced while sizable mobilities in the 2D semiconductors are maintained. Thus, in recent years considerable research efforts have focused on 2D FETs and explored various 2D semiconductors and their properties. However, the key challenge of finding suitable gate insulators for 2D FETs has yet received little attention. In this paper, criteria are formulated for identifying suitable gate insulators for reliable 2D FETs. The criteria are grouped into three main categories, these are scaling requirements, reduction of insulator-related charge traps, and technological requirements for the insulator deposition. In addition, possible candidates for gate insulators for 2D FETs are evaluated with respect to the formulated criteria, and important research questions for future investigations are identified.

Premium content

A Flexible and Inherently Self-Consistent Methodology for MOL/BEOL/MIMCAP TDDB Applications with Excessive Variability-Induced Degradation

Downloads

Next from IRPS 2022

Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES