United States

This paper will discuss how deep data analytics based on Universal Chip Telemetry™ (UCT) offers a new approach to lifecycle health and performance monitoring in advanced electronics. By combining on-chip monitoring with machine learning inference in the cloud and edge, production quality is improved through advanced latent defect detection, while lifetime reliability is increased through degradation monitoring and predictive fault detection.

IRPS 2022

Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics

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**2022 IEEE International Reliability Physics Symposium has gone mobile!**

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

New multi-layer ALD HfO2/Al2O3/HfO2
laminate film with a capacitance density 8.3 fF/um2 is evaluated in a MIM capacitor, in 65nm node process, for emerging applications in the automotive space which require higher use voltage and temperature than CMOS logic and DRAM applications. Apart from the typical considerations such as leakage current, capacitance linearity etc. the dielectric relaxation current behavior is also studied. We have performed a thorough reliability study on these films and demonstrate that they meet the stringent requirements for automotive safety applications.

High-k MIM dielectric reliability study in 65nm node

Simulations based on first-principle modeling of material structural features determining electrical properties of a CNT memory cell allow to identify a range of operation conditions delivering desirable device characteristics. This approach designates the path for optimization of the CNT memory device structure to meet the performance requirements.   

Combining measurements and modeling/simulations analysis to assess carbon nanotube memory cell characteristics

Contacts stability versus thermal budget is a major concern in 3D sequential integration. We experimentally investigate the thermal stability of n-type contacts on Si and p-type contacts on SiGe in terms of specific contact resistivity (ρc). An improved ρcn performance featuring lower magnitude and better thermal stability has been demonstrated for Ti silicide contacts on n+-Si with Ge pre-amorphization implantation (PAI). For p-type contacts, it is found that Ni has lost its high work function advantage on p++-SiGe and Ti germanosilicide contacts show ρcp outperformance. CMOS contact scheme based on single Ti instead of dual Ti and Ni has hence been evidenced to be more suitable for 3D sequential integration.

Investigation on Contacts Thermal Stability for 3D Sequential Integration

This paper studies the use of 1-selector-1-resistor (1S1R) devices as the cross-point components in a crossbar array for deep neural network (DNN) training. Two training algorithms—minibatch gradient descent (MBGD) and a low-rank approximation to MBGD—are evaluated with compact models of ovonic threshold switching (OTS) selectors considering several reliability issues, and resistive random-access memory (ReRAM), a type of emerging non-volatile memory (NVM) device. We explore various reliability concerns of the OTS selectors including the low on-state conductance, threshold voltage variation, and internal voltage offset, etc. and propose corresponding techniques to overcome the reliability challenges.

Effect of OTS Selector Reliabilities on NVM Crossbar-based Neuromorphic Training

In this paper, the long term data retention characteristics consisting of three main charge loss mechanisms, detrap, trap-assisted tunneling (TAT), and lateral migration (LM), are investigated in charge trap (CT) 3D NAND flash memory. Three mechanisms were completely separated through experiment design, and each activation energy (Ea) was extracted with Arrhenius model well. The detrap mechanism shows the largest Ea, followed by LM and TAT mechanisms. It is interesting that the contribution rate (CR) of each mechanism is related to time-constant (t) in the early part of bake time, and depends on the final charge loss in the latter part of bake time. It is inferred that the retention bottleneck is low program level state at high temperature and is high program level state at low temperature. TAT mechanism dominates the final charge loss regardless of temperature region and program level state. In addition, an effective method is proposed to suppress the LM effect.



Investigation of Retention Characteristics in a Triple-level Charge Trap 3D NAND Flash Memory

This work shows that the complex dynamic-RON characteristics observed for highly scaled HEMT devices results from the similar capture/emission activation energies of the defects present in different epitaxial layers. This work also (i) presents an optimized experimental scheme for a detailed analysis of the different charge-trapping mechanisms in GaN-on-Si HEMTs, (ii) describes the charge-trapping kinetics over a wide range of temperatures using capture/emission time (CET) maps, and (iii) models the defect energy distribution in the AlGaN barrier by analytically deriving the 2D potential profile in the access region and combining it with the results from CET maps.

Interpretation and modelling of dynamic-RON kinetics in GaN-on-Si HEMTs for mmWave applications

Scaled (LG = 0.1 μm) GaN HEMT technology is currently pursued for high-frequency applications (such as 5G), requiring high current/speed and blocking capability. However, traps introduced with intentional Fe doping yield time-dependent breakdown voltage (VBR), seriously affecting reliability. Here, we investigate the role of Fe traps by pulsed I-V characterization performed at different pulse durations (TOFF). A TOFF-dependent VBR is observed on tested devices and is ascribed to the time-dependent occupancy of deep acceptors in the buffer layer. More specifically, the decrease in VBR for short pulses is attributed to the increased leakage due to the reduced ionization of Fe-traps. This interpretation is supported by 2D numerical simulations.

Fe-Traps Influence on Time dependent Breakdown Voltage in 0.1 µm GaN HEMTs for 5G applications

On-chip degradation monitoring enables reliable recycling of chips in the context of circular economy by assessing their degradation and thereby inferring their remaining lifetime. Implementations of such monitors have already been presented typically relying on ring-oscillator-based circuits to evaluate degradation undergone by ICs. However, these approaches are not able to distinguish between the physical degradation and the time since fabrication and they can be tampered with high temperature annealing. In this work we present a new concept of degradation monitor circuit, which can obtain the age of the chip and detect if the chip has undergone tampering through high-temperature annealing.

A Ring-Oscillator-based Degradation Monitor Concept with Tamper Detection Capability

Owing to its high power, high efficiency, high gain and high frequency capabilities RF-GaN technology has not only dominated satellite, aerospace and telecom industry but also been tapped as the most promising candidate for 5G technology extension to millimeter wave (MMW) applications. Excellent device performances with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 % have been demonstrated by Wolfspeed's 5G-MMW capable 28 V, 150-nm gate length (V5) GaN on SiC technology. In this work we show the comprehensive DC (both on and off state) and RF reliability assessment and lifetime projection (both DC and RF) of such MMW capable 28 V rated 150-nm gate length process technology (G28V5). The on-state and off-state results coupled with the reliability without hermiticity (RWOH) capability and intrinsic reliability assessment up to 31.5 GHz demonstrate the maturity and reliability of V5 technology as a true candidate for MMW applications.

DC & RF Reliability Assessment of 5G/mmW capable GaN HEMT Process

Fault injections and attacks on an integrated circuit (IC) chip using a variety of physical measures are reviewed. Laser fault injection (LFI) is highlighted for the essential vulnerability on the backside of an IC chip in flip-chip packaging. On-chip voltage waveform monitoring characterizes the voltage peaks induced by LFI and establishes the detection scheme against LFI attacks. The backside buried metal (BBM) technique is deployed by preventive measures for shielding from laser exposure, for avoidance and also waring of invasive laser attacks. The alleviation of backside LFI is proven by Si experiments with on-chip waveform monitoring.

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Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics

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