France

InP DHBTs are well known for their capability to provide both high cutoff frequencies together with high breakdown voltage. III-V Lab has developed for several years very high-speed and high swing integrated circuits based on this technology. In this presentation, we will focus on the technological features of present 0.7-μm InP/GaInAs DHBT exhibiting around 400-GHz fT and fMAX, as well as a breakdown voltage above 4.5 V and a high dissipated power above 35 mW at peak fT. The relaxed emitter width enables to work at moderate current densities and ensure a very high fabrication yield and performance homogeneity on 3’’ wafer. More compact 0.5-µm DHBT and circuit oriented device generation allowing above 500 GHz fmax is also presented. We will demonstrate that our technology is also compatible with the fabrication of GaAsSb-based InP DHBT and a comparison of the key figures of merits between Type-I and Type-II InP DHBTs fabricated in a same process will be presented.

ESSCIRC ESSDERC Educational Events

InP DHBT technology at III-V Lab

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double heterojunction bipolar transistor

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The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

This tutorial is to present how chips can be protected against fault injection attacks by using internal sensors.
It gives an overview of sensors to detect different types of fault injection techniques like electromagnetic and laser shots. It presents a generic digital sensor and gives some perspectives for future research topics.

ON Chip Security Sensors

Recent work has shown that architectural isolation can be violated through software side channel attacks that exploit microarchitectural performance optimizations such as speculation to leak secrets. While turning off microarchitectural optimizations can preclude some classes of attacks, we argue that performance and security do not have be in conflict, provided processors are designed with security in mind.

We advocate designing processors to support enclaves, which are processes with an associated security policy, and espouse a principled hardware/software co-design approach to eliminating entire attack surfaces relevant to the security policy through microarchitectural isolation, rather than plugging attack-specific privacy leaks. As a case study of this approach, we describe both in-order and speculative processor designs that offer strong provable isolation of software modules running concurrently and sharing resources, even when large parts of the operating system are compromised. Open-source implementations of these processors will allow security properties to be independently verified. Finally, we describe the current limitations of this approach and future opportunities for research.

Towards Secure High-Performance Computer Architectures

The threats of side-channel attacks are getting non-trivial because they can be done by relatively low-cost equipment in a non-destructive manner. In the last few decades, a variety of side-channel attacks have been reported. Even today, the attack capability are evolving with new techniques such as machine learning. This talk will start with an overview of researches on side-channel attacks, and then introduce the-state-of-the-art side-channel attacks and countermeasures including a novel circuit-level countermeasure that makes it possible to prevent advanced side-channel attacks.

Secure Cryptographic Circuit Design against Side-Channel Attacks

And overview of what security means for ST products, the resulting embedded-security R&D themes, key considerations when doing hardware-security-design for high-volume quality manufacturing, and a short overview of other important emerging embedded security challenges.

Embedded security: A silicon provider's perpective

In this talk, we present state-of-the-art attack and defense methodologies that are based upon machine learning and hardware systems. In particular, we present three works, (i) ProFlip, (ii) HASHTAG and (iii) GenUnluck. (i) ProFlip is the first targeted Data Poisoning/Model Trojan attack framework that can divert the prediction of the DNN to the target class by progressively identifying and flipping a small set of bits in the model parameters. (ii) HASHTAG is the first framework that enables high-accuracy detection of fault-injection attacks on Deep Neural Networks (DNNs) with provable bounds on detection performance. (iii) GenUnluck is the first efficient framework, based upon Genetic Algorithms and AI, that has been shown to break several contemporary logic locking algorithms.

Attacks and Defenses rooted in Machine Learning and Hardware Systems

Side-Channel-Attack Tolerant Crypto Engines

This tutorial presentation overviews power side-channel leakages and attacks on integrated circuit chips featuring cryptographic cores. The knowledge are linked among on-board electromagetic measurements, on-chip voltage monitoring, and full-system level power noise simulation techniques for the in-depth understanding of power side-channel leakage problems.

Side-channel Leakages, Attacks and Simulation for Hardware Security

Some Insights in Automated Netlist Reverse Engineering

System-on-Chip platforms have been increasingly extended with trusted computing functionality to provide strong protection for sensitive software applications through enclaves that only require trust in the hardware and minimal software components. However, the deployed enclave architectures are still suffering from various shortcomings such as the lack of secure I/O, or being vulnerable to side-channel attacks. Thus, recent research works propose new enclave architectures with more comprehensive threat models and advanced security features. A majority of these solutions is being developed on the open RISC-V architecture. In this paper, we present a brief overview of the RISC-V-based enclave architectures, discuss their features, limitations and open challenges.

InP DHBT technology at III-V Lab

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ON Chip Security Sensors

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InP DHBT technology at III-V Lab

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Next from ESSCIRC ESSDERC Educational Events

ON Chip Security Sensors

Similar lecture

Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads