Spain

The current dependency of Artificial Intelligence (AI) systems on Cloud computing implies higher transmission latency and bandwidth consumption. Moreover, it challenges the real-time monitoring of physical objects, e.g., the Internet of Things (IoT). Edge systems bring computing closer to end devices and support time-sensitive applications. However, Edge systems struggle with state-of-the-art Deep Neural Networks (DNN) due to computational resource limitations. In this proposal, an introduced framework combines the Edge-Cloud architecture concept with BranchyNet advantages to support fault-tolerant and low-latency AI predictions. The implementation and evaluation of this framework allow assessing the benefits of running Distributed DNN (DDNN) in the Cloud-to-Things continuum. Compared to a Cloud-only deployment, the results obtained show an improvement of 45.34% in the response time. Furthermore, this proposal presents an extension for Kafka-ML that reduces rigidness over the Cloud-to-Things continuum managing and deploying DDNN.

AEiC 2021 - 25th Ada-Europe International Conference on Reliable Software Technologies

A low-latency and fault-tolerant framework for distributed and deep neural networks over the cloud-to-things continuum

[![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/359fc42963be9dbef8d1acac451d7c3e.png)](https://www.ada-europe.org/conference2021)

### Welcome Message from our Co-Chairs

Through this message, we want to give you our warmest welcome to the 25th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2021). The special circumstances we all go through have made the conference a virtual event. Nonetheless, this will allow us to take advantage of the benefits of this format by using the Underline.io platform that allows remote participation of speakers and attendees and a virtual exhibition.
The platform will also provide a virtual space through Gather.Town to facilitate social interaction among participants, which, in addition to presenting state of the art research results, is one of the most important goals of a conference. This platform will hold various social events together with breaks and a poster session. 

The conference schedule includes a four-day program and exhibition from Monday to Thursday, with parallel tutorials on Monday, and keynotes, technical sessions and a Work-in-Progress session on the remaining three days. The technical sessions include the presentations of 13 journal-track papers, 5 industrial presentations and 6 invited talks on leading topics on reliable software technologies. The program will be completed with three outstanding keynotes that will delight the participants.

The main conference activities will be from 13:00 to 18:00 Central European Summer Time (CEST) to allow participants from America to Central Asia to attend to the conference sessions. Virtual social events are scheduled at the beginning and the end of each day. We encourage you to participate in these activities as well as visiting the exhibition. We look forward to meeting you virtually in June 2021!

**J. Javier Gutiérrez and Mario Aldea Rivas**
 // AEiC 2021 Program Co-Chairs

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/609207a715bd5da2ea56e9a32b0d17ae.png)
![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/5bd0a9396b4c6903d0ca52825b81fbe6.png)




Please register with AEiC to be able to enter the conference on Underline.io. If you have already registered, please login to Underline.io to be able to see full conference content. In case you do not have an Underline account, please create one. Thank you 

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The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

Spazio IT has been working on the Independent Software Verification and Validation of several codebases, some written in Ada, others in C/C++ and more recently also in Python; in all cases Spazio IT has used static analysis techniques and tools facilitating code inspection. Static analysis has always proven to be beneficial, but depending on the programming language, its advantages have emerged in different areas and namely: metrics and structural analysis for Ada, bugs finding at execution/semantic level for C/C++ and errors finding at compilation/syntactical level for Python. The paper presents first some general considerations on static analysis, then it concentrates on static analysis specifically applied to Ada, C/C++ and Python codebases. Finally, the paper describes Spazio IT future activities in the area of static analysis.

Static analysis for Ada, C/C++ and Python: different languages, different needs.

This paper compares the origins, features, and status of two different tools intended to facilitate static analysis of Ada programs: ASIS and LibAdalang. It stresses the differences in principles, features,and intended usages, and shows use cases where each is more appropriate.

ASIS vs. Libadalang: a comparative assessment

Ghost entities and optimization

Vendor presentation: Vector

Augmented Reality (AR) technologies are used as human-machine interface within various types of safety-critical systems. In order to avoid unreasonable risk, it is required to detect new types of dependability threats (faults, errors, failures). These dependability threats could be introduced within the systems by new technologies. Based on the context of ImmerSAFE project and due to spread of AR technologies we target AR. In our previous work, we have designed extensions for SafeConcert metamodel to capture AR-related dependability threats (focusing on faults and failures). The extensions provide modeling and analysis capabilities that can be used for modeling and analyzing \hl{different entities and their behaviors} in AR-equipped socio-technical systems. \hl{Despite provision of various modeling and analyzing techniques, there has been no detailed investigation of providing an integrated framework for risk assessment in AR-equipped socio-technical systems.} In this paper, we provide an integrated framework based on our proposed extensions. In addition, we design and execute a case study, with our industrial partners, active in the automotive domain. We aim at validating modeling and analysis capabilities of the framework and finding out if the proposed extensions would be helpful in capturing system risks caused by new AR-related dependability threats. We conduct qualitative analysis based on Concerto-FLA analysis technique, which is an analysis technique for socio-technical systems included in CHESS toolset.

A low-latency and fault-tolerant framework for distributed and deep neural networks over the cloud-to-things continuum

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Static analysis for Ada, C/C++ and Python: different languages, different needs.

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