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Early verification and validation (V&amp;V) of design artifacts is one of the main promises of model-based software design. The kind of V&amp;V and possible level of automation depends on the degree of formalization. Semi-formal languages such as UML or SysML facilitate structuring design artifacts and describing them in agreed-upon terms but require additional extension to reach the level of rigour that permits code generation and formal verification. Simulation-oriented languages such as Simulink® and Stateflow® contain sufficient details to allow execution of the model and generation of program code for implementation. In both cases, simulation, formal verification, and code generation require precise definition of language elements. As the goals of and tooling for each of these tasks are different, the tool developers must often define the semantics multiple times and at different levels of detail. This in turn raises the question of whether the language definition used in verification and simulation matches the one used for code generation. This work-in-progress talk will demonstrate model verification with both CodePeer and SPARK Pro tools on simple examples. We will explain how analysis of Ada/SPARK is expected to help C developers. Finally, we cover limitations of the approach and ongoing work.

AEiC 2021 - 25th Ada-Europe International Conference on Reliable Software Technologies

Using Ada for model verification

2021 Annual Conference of the North American Chapter of the Association for Computational Linguistics.

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NAACL 2021

Early verification and validation (V&V) of design artifacts is one of the main promises of model-based software design. The kind of V&V and possible level of automation depends on the degree of formalization. Semi-formal languages such as UML or SysML facilitate structuring design artifacts and describing them in agreed-upon terms but require additional extension to reach the level of rigour that permits code generation and formal verification. Simulation-oriented languages such as Simulink® and Stateflow® contain sufficient details to allow execution of the model and generation of program code for implementation. In both cases, simulation, formal verification, and code generation require precise definition of language elements. As the goals of and tooling for each of these tasks are different, the tool developers must often define the semantics multiple times and at different levels of detail. This in turn raises the question of whether the language definition used in verification and simulation matches the one used for code generation. This work-in-progress talk will demonstrate model verification with both CodePeer and SPARK Pro tools on simple examples. We will explain how analysis of Ada/SPARK is expected to help C developers. Finally, we cover limitations of the approach and ongoing work.

technical paper

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### Welcome Message from our Co-Chairs

Through this message, we want to give you our warmest welcome to the 25th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2021). The special circumstances we all go through have made the conference a virtual event. Nonetheless, this will allow us to take advantage of the benefits of this format by using the Underline.io platform that allows remote participation of speakers and attendees and a virtual exhibition.
The platform will also provide a virtual space through Gather.Town to facilitate social interaction among participants, which, in addition to presenting state of the art research results, is one of the most important goals of a conference. This platform will hold various social events together with breaks and a poster session. 

The conference schedule includes a four-day program and exhibition from Monday to Thursday, with parallel tutorials on Monday, and keynotes, technical sessions and a Work-in-Progress session on the remaining three days. The technical sessions include the presentations of 13 journal-track papers, 5 industrial presentations and 6 invited talks on leading topics on reliable software technologies. The program will be completed with three outstanding keynotes that will delight the participants.

The main conference activities will be from 13:00 to 18:00 Central European Summer Time (CEST) to allow participants from America to Central Asia to attend to the conference sessions. Virtual social events are scheduled at the beginning and the end of each day. We encourage you to participate in these activities as well as visiting the exhibition. We look forward to meeting you virtually in June 2021!

**J. Javier Gutiérrez and Mario Aldea Rivas**
 // AEiC 2021 Program Co-Chairs

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Global static scheduling (one scheduling table generated off-line per processor) for Mixed Criticality (MC) systems demonstrate excellent results in terms of acceptance ratio and number of preemptions. But, no practical implementation and empirical evaluation have been presented yet for multi-processors systems. In this paper, we present two contributions on the implementation of global static schedulers for MC systems to enforce low latency mode changes. This work interest is illustrated scheduling scheduling tables produced by GMH_MC_DAG, a meta-heuristic to compute schdeduling tables for multi-periodic Directed Acyclic Graphs of Mixed Criticality tasks with multiple criticality level.

Contributions to the implementation of global schedulers for mixed-criticality systems

The use of hardware caches became essential in modern embedded systems to address the speed gap between processor and memory. In such systems, cache-related preemption delay (CRPD) may represent a significant proportion of task execution time. Addressing this delay in scheduling simulation of these systems stays an open and under-examined problem. Assumptions are often made to simplify the computation model used in simulation and capture the worst-case effect. Nevertheless, they can introduce situations in which scheduling simulation is considered not only pessimistic but also non-sustainable. In this article, we discuss the problem and propose a less pessimistic CRPD computation model that allows sustainable scheduling simulation regarding the capacity parameter. With the proposed model, a system that is schedulable with simulated worst-case execution times remains so when these parameters are reduced. These results improve the applicability of scheduling simulation in the early verification stage for systems with caches. Experiments conducted with our CRPD computation model show a 5% to 12% improvement of schedulability task set coverage and a 30% to 50% reduction of preemption cost with regard to existing CRPD computation models. An integration in a scheduling simulator and a performance evaluation are also realized for the proposed model.

Feasibility interval and sustainable scheduling simulation with CRPD on uniprocessor platform

Since 1973, Earliest Deadline First (EDF) uniprocessor scheduling has been known to be superior to its Rate Monotonic (Fixed-Priority, FPS) counterpart. Such superiority manifested in optimality, the capacity of EDF to feasibly sustain full utilization, which FPS can only achieve in certain favorable circumstances. In 2005, further research results argued that EDF's superiority would also extend to finer-grained performance indicators, such as preemption count, release and response-time jitter, resilience to transient overload. Recent work allowed EDF uniprocessor scheduling to be used in place of default FPS in Ada Ravenscar systems with unchanged application code: this development provides an interesting and practical avenue for empirical EDF-to-RM performance comparisons in an especially lean and efficient embedded setting. We leveraged that opportunity to develop a toolbox that enables quantitative comparison of EDF-to-RM uniprocessor scheduling with lightweight run-time tracing and offline analytic. In this work we present that toolbox and illustrate results we obtained with it, which shed new light on the presumed superiority of EDF to RM.

Removing bias from the judgment day: A Ravenscar-based toolbox for quantitative comparison of EDF-to-RM uniprocessor scheduling

This talk introduces a formal framework for describing the relationship between a criticality-aware scheduler and a set of application tasks that are assigned different criticality levels. The exposition employs a series of examples starting with scheduling simple jobs and then moving on to mixed-criticality tasks. The proposed formalism extends the rely-guarantee approach, which facilitates formal reasoning about the functional behaviour of concurrent systems, to address real-time properties.

Formally specifying the behaviour of a mixed criticality scheduler

Autonomous vehicles, such as drones, are gaining great popularity due to their usability and versatility. Nowadays, a significant number of them operate using open source software, such as Robot Operating System (ROS) and the de facto standard MAVLink communication protocol, as they are free and many of them are reusable enough that they can be deployed in various different vehicles. Although these technologies offer a wide variety of resources, using them requires a reasonable background of programming and system engineering. Often, this is not achievable by common drone end-users in the short-term, as they would need to acquire a considerably large amount of know-how before working on specific domains. However, a graphical Domain Specific Modelling Language (DSML) might provide a shortcut to design drone missions using already known concepts to the end-users (or, at least, ones easier to learn). Pursuing this shortcut, RoBMEX is presented as a top-down methodology based on a set of domain specific languages able to enhance the autonomy of ROS-based systems, by allowing the creation of missions graphically, and then generating automatically executable source codes conforming to the designed missions.

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