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Design Technology Co-optimization (DTCO) has become a critical part for new technology development and applications.  For high end and critical application products, reliability co-optimization is an important integral part of DTCO.  This tutorial focus on the interconnect reliability optimization considerations for chip design.  Discussions will be made from understanding the intention and limitation of various design guidelines &amp; reliability limits to identifying critical areas and robust layouts for different interconnect reliability mechanisms for chip design.

IRPS 2024 Tutorials and YIR

Interconnect Reliability for Chip Design

Design Technology Co-optimization (DTCO) has become a critical part for new technology development and applications.  For high end and critical application products, reliability co-optimization is an important integral part of DTCO.  This tutorial focus on the interconnect reliability optimization considerations for chip design.  Discussions will be made from understanding the intention and limitation of various design guidelines & reliability limits to identifying critical areas and robust layouts for different interconnect reliability mechanisms for chip design.

tutorial

**IRPS 2024 Tutorials were held in Dallas, Texas from April 14 to 15, 2024. The IRPS Reliability Year in Review (YIR) session consisted of three presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It was a nice augmentation to the tutorials sessions immediately preceding and attendees were able to obtain keen reliability insights in short amount of time.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**
Please save the zip file locally and click the "start.pdf" to view the file. 

**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Hot-carrier degradation (HCD) is a major reliability concern in current and upcoming CMOS technology nodes. In this tutorial, we describe the properties and physical understanding of this FET aging mechanism. We then briefly review past HCD models and explain in depth the modeling of HCD for current technologies. We also address the related problem of self-heating and its interaction with HCD. Additionally, we review different strategies which are used to counteract HCD.

Hot-carrier Degradation in MOS Transistors

5/6G implementation will enhance mobile broadband service in more ways than the user can imagine. 5/6G will create a unified wireless network operating on a global scale, enabling uses far beyond just consumer-oriented devices. Manufacturers must validate reliability to standards of emerging industry as well as standards already in traditional markets. How can the technical team arm sales and marketing with data to convince customers that un-fielded products will work reliably in the intended environment?

From Fabrication to Field: The Importance of Semiconductor Reliability Testing in the Age of Wireless Transformation

GaN utilization in RF communications systems is expanding. Reliability assessment of GaN largely follows proven techniques of static stress conditions to quantify acceleration mechanisms predicting long term degradation, along with short term transient stress conditions. These test methods do not assess multiple stress conditions’ impact and interaction during operation of complex RF/microwave/mmWave circuits. This tutorial presents fundamental RFOLT methods, discusses the complex stress conditions introduced and the value of RFOLT assessing device and circuit reliability.

GaN RFOLT for 5G/6G Applications

PID is discussed from the fundamentals to the complex “well charging”. A full description of the PID failure mechanism sets a common understanding for the need of a comprehensive qualification procedure including antenna ratio definition, test structures, stress methods, key analysis parameters for silicon-bulk and SOI technologies. Well charging is under discussion to define antenna design rules for a reliable productive design rule checker. Two competing methods are described from literature with brand-new findings. 

Plasma Induced Damage (PID): From Basics to Complex Well Charging

To meet the growing demand for integrated circuits (ICs) in increasingly complex and demanding applications, the semiconductor industry has evolved dramatically during the past few decades. Military, space, and avionic electronics must survive harsh environmental conditions, requiring highly reliable specialized packaging like 2.5D/ 3D hetero integration (HI) for greater functionality, device density, and speed. Thus, cross-coupled chip-package-board interactions (CPBIs) result from the proximity of a wide variety of active and passive components and material stacks and processes. This tutorial will provide insights into the emerging electrical reliability challenges typical of a 2.5D/3D packaged IC and offer potential solution schemes to ensure reliable IC operation under the most stringent conditions.

Electrical Chip-Package-Board Reliability of 2.5D/3D Heterogeneously Integrated Systems

We review the drift of MOS devices parameters and the MOS device gate dielectric breakdown in off-state mode. Non-conducting hot carrier may induce significant drift of digital and I.O. devices in overdrive conditions, High voltage asymmetrical devices, power switches as well as RF devices.

Gate dielectric breakdown is critical not only as a parasitic phenomenon occurring while performing accelerated non-conducting HCI stress but also can be a limiting factor for High Voltage asymmetrical MOS devices.

Effect of OFF-State Stress on CMOS Devices

The growing complexity of today’s automotive vehicles goes side by side with increasingly stringent and multifaceted safety requirements. Just like electromechanical systems in a car, semiconductor components now need to demonstrate high levels of reliability against a variety of failure modes, out of which radiation effects could arguably be among the most unpredictable at system level. While cosmic-ray induced errors may be rare at sea level, the sheer number of land vehicles in a manufacturer’s….

New Industrial Radiation Paradigms for LEO Satellite Constellations, Full Autonomous Car Driving and Sovereign 3D Chiplets

Recent advances in automotive SOCs, AI accelerators, and HPC engines in data centers have led to an explosion in the adoption of emerging technology nodes and 3DIC/chiplet packages. We will discuss the resiliency challenges for these emerging SOCs, and optimizing the SOC health using prognostics, test and analytic solutions, utilized for managing silicon lifecycle (SLM) for improving quality and yield; and also address aging and degradation challenges for improved RAS and functional safety.

Silicon Health &amp; Lifecycle Management, for Data Center and Automotive

3D NAND flash memory is pivotal for large-scale data storage and finds application in aerospace and defense. However, the harsh environmental conditions pose several reliability challenges for 3D NAND, including radiation-induced data corruption and cross-temperature reliability issues. In this tutorial, I will introduce a framework to understand radiation effects on flash memory and present three techniques—electrostatic shielding, defect engineering, and watermark storage—to mitigate radiation effects on commercial 3D NAND.

Reliability Challenges of 3D NAND Flash Memory in Harsh Environments

Moving along in parallel with the emergence of ever stronger artificial intelligence, the development of next generation AI hardware which harnesses the unique properties of physical systems, beyond classical digital computing, has been continuously evolving. AI scientists, in the pursuit of lower energy costs and smaller model sizes, have already been willing to make compromises on model accuracy for improved performance in edge applications. In the case of novel AI hardware, trading off the reliability of digital systems for the reduced energy cost of analog and neuromorphic systems, presents new opportunities for exploring the same technology space as current efforts in edge inference. In this lecture, we will briefly review the foundations of modern AI from the perspective of loss function minimization, and explore how physical systems mathematically interact with this loss landscape. In doing so, we will explore how scientists this past year have been balancing the tradeoffs from device defects, analog noise, variability, and other phenomenon to develop next generation systems for AI inference as well as how to understand these developments using the mathematical tools employed by AI scientists. 

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Hot-carrier Degradation in MOS Transistors

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Next from IRPS 2024 Tutorials and YIR

Hot-carrier Degradation in MOS Transistors

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

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