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Resistive switching memory (RRAM) technology is a promising resource in the landscape of neuromorphic computing applications. In fact, RRAM can provide a convenient primitive for matrix-vector multiplication with a strong impact on the acceleration of Deep Learning. However, RRAM is affected by intrinsic conductance variations which might cause short- and long-term reliability issues. This tutorial will present a multiscale approach, ranging from the device to the circuit level, to mitigate those issues for accelerator design.

IRPS 2024 Tutorials and YIR

Reliability of RRAM Technology in the Context of Neuromorphic Applications

tutorial

**IRPS 2024 Tutorials were held in Dallas, Texas from April 14 to 15, 2024. The IRPS Reliability Year in Review (YIR) session consisted of three presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It was a nice augmentation to the tutorials sessions immediately preceding and attendees were able to obtain keen reliability insights in short amount of time.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**
Please save the zip file locally and click the "start.pdf" to view the file. 

**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Defect localization is key to device improvement, yield management, and reliability fail characterization.  How do you isolate defects when your fails are blowouts? How does one choose an FA technique form the alphabet soup of techniques? This tutorial will offer an overview of a wide variety of electron, ion, and laser-based fault isolation techniques from decades of fab experience and cutting-edge technique development in microscopy development. 

Defect Localization Methods for Device Characterization and Yield Management

This tutorial aims at presenting an overview of degradation phenomena that lead to dielectric breakdown. We discuss how dielectric degradation can be observed and show possible consequences for device operation. An important aspect of TDDB is a correct description of its statistics, that can be derived from individual defect generation dynamics. We look at modeling approaches and ways of calculating the time-to-breakdown. We also discuss differences and similarities of breakdown in FEOL, MEOL and BEOL.

Understanding and modeling Time-Dependent Dielectric Breakdown

Technology Computer Aided Design (TCAD) tools are well established for modeling semiconductor fabrication processes, and device operations. This tutorial provides an overview how TCAD can is for modelling of various reliability issues, including mechanical stresses introduced during manufacturing process or device operations, Electrostatic Discharge (ESD), latch up/junction breakdown, Hot Carrier Degradation (HCD) and Negative Temperature Bias Instability (NTBI) and Time Dependent Dielectric Breakdown (TDDB), modeling of charge loss mechanics in 3D NAND memories, and others.

TCAD for Reliability

Two-dimensional (2D) materials possess various intriguing properties, making them promising building blocks for future nanoelectronics. For example, 2D semiconductors offer sizable mobilities and high on-currents in thin layers, allowing for excellent gate control in scaled transistors. Nonetheless, to bridge the gap between current device prototypes and commercial applications, multiple challenges must be overcome, including identifying gate stacks that are both scalable and allow for reliable operation throughout the device’s lifetime.

Reliability of Nanoelectronics based on Two-Dimensional Materials

In this tutorial, I will give a brief introduction to reliability and failure analysis fundamentals; review key reliability aspects for SiC devices such as bias temperature instability, bipolar stability due to Shockley stacking faults, gate oxide reliability, humidity effects, reverse bias, single event burnout and power cycling; illustrate mission profile analysis techniques; review essential failure analysis techniques such as fault detection, FIB/SEM and EBIC; and review the latest industry consortia standards and guidelines.

SiC Device Reliability and Failure Analysis

Design Technology Co-optimization (DTCO) has become a critical part for new technology development and applications.  For high end and critical application products, reliability co-optimization is an important integral part of DTCO.  This tutorial focus on the interconnect reliability optimization considerations for chip design.  Discussions will be made from understanding the intention and limitation of various design guidelines & reliability limits to identifying critical areas and robust layouts for different interconnect reliability mechanisms for chip design.

Interconnect Reliability for Chip Design

Hot-carrier degradation (HCD) is a major reliability concern in current and upcoming CMOS technology nodes. In this tutorial, we describe the properties and physical understanding of this FET aging mechanism. We then briefly review past HCD models and explain in depth the modeling of HCD for current technologies. We also address the related problem of self-heating and its interaction with HCD. Additionally, we review different strategies which are used to counteract HCD.

Hot-carrier Degradation in MOS Transistors

5/6G implementation will enhance mobile broadband service in more ways than the user can imagine. 5/6G will create a unified wireless network operating on a global scale, enabling uses far beyond just consumer-oriented devices. Manufacturers must validate reliability to standards of emerging industry as well as standards already in traditional markets. How can the technical team arm sales and marketing with data to convince customers that un-fielded products will work reliably in the intended environment?

From Fabrication to Field: The Importance of Semiconductor Reliability Testing in the Age of Wireless Transformation

GaN utilization in RF communications systems is expanding. Reliability assessment of GaN largely follows proven techniques of static stress conditions to quantify acceleration mechanisms predicting long term degradation, along with short term transient stress conditions. These test methods do not assess multiple stress conditions’ impact and interaction during operation of complex RF/microwave/mmWave circuits. This tutorial presents fundamental RFOLT methods, discusses the complex stress conditions introduced and the value of RFOLT assessing device and circuit reliability.

GaN RFOLT for 5G/6G Applications

PID is discussed from the fundamentals to the complex “well charging”. A full description of the PID failure mechanism sets a common understanding for the need of a comprehensive qualification procedure including antenna ratio definition, test structures, stress methods, key analysis parameters for silicon-bulk and SOI technologies. Well charging is under discussion to define antenna design rules for a reliable productive design rule checker. Two competing methods are described from literature with brand-new findings. 

Reliability of RRAM Technology in the Context of Neuromorphic Applications

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Defect Localization Methods for Device Characterization and Yield Management

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Reliability of RRAM Technology in the Context of Neuromorphic Applications

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Next from IRPS 2024 Tutorials and YIR

Defect Localization Methods for Device Characterization and Yield Management

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads