United States

NBTI of IGZO TFTs is studied using diverse devices and conditions. Four main characteristics are observed: V th shift is almost independent of V g_stress, and shows a large activation energy and a steep time kinetic, while the relaxation rate decreases with increasing temperatures. Using TCAD and modelling, these peculiar features can be explained by an oxide-field-dominated hydrogen release at gate side of the gate-dielectric, inducing additional doping and the negative V th shift.

IRPS 2024 Main Conference

Fundamental understanding of NBTI degradation mechanism in IGZO channel devices

oxide-field-driven hydrogen release

negative shift

nbti

igzo

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

We report distinct breakdown mechanisms in CVD monolayer MoS2 FET devices for the first time mediated by either voltage or currents in devices. A detailed analysis of the breakdown physics explains the operational effects led shortcomings expected in downscaled devices. Operating short channel TMDs devices would be tricky owing to the dipole moment making it imperative to address the piezoelectric response related drifts in search of reliable performance.

Decoupling Current and Voltage Mediated Breakdown Mechanisms in CVD MoS2 FETs

In this work we develop an ALD grown IGZO channel analyze physical mechanism and reliability governed by channel defects and demonstrate interface-engineered IGZO (IFE-IGZO)-based transistor with high mobility (µ) and superior reliability.

Low-PBTS defect-engineered high-mobility metal-oxide BEOL transistors

A simplified methodology to link CW (Continuous Wave) RF stresses to complex mission profiles is presented in order to compare the lifetimes of different 40nm PDSOI Power Amplifier (PA) cells, versus bias and under different 5G-FR2 modulation profiles. The best lifetime is achieved when using the most complex 5G modulation due to output power/linearity constraints. VT drift correction is also identified as a powerful tool to increase transistor HCI lifetime under PA operation.

A Methodology to address RF aging of 40nm CMOS PA cells under 5G mmW modulation profiles

A robustness assessment has been performed for 77GHz power amplifier. First, a study performed at device level with RF stress illustrates the process capability to support HCI for aggressive mission profile, then secondly a robust setup OLT has been used to carry out 500h stress on several samples. The spread observed on degradation can be explained with Monte Carlo simulation of the complete TX chain. Adequation with ageing model are rather good.

Robustness assessment through 77GHz Operating Life Test of power amplifier for radar application in 28nm FD-SOI CMOS

This study detects recycled ICs by assessing aging-related degradation in intrinsic I/O pad transistors. We do this by: (i) configuring Arm Cortex-M0+ microcontrollers (32 and 72 MHz) to access individual I/O buffer transistors (NMOS/PMOS), (ii) examining NBTI/PBTI degradations in these PMOS and NMOS transistors under AC and DC stress, and (iii) developing an algorithm to distinguish between recycled (with estimated age) and new ICs based on the degradation rate in the NMOS/PMOS under stress.

Validating Supply Chain against Recycled COTS ICs using I/O Pad Transistors: A Zero-Area Intrinsic Odometer Approach

This work reports a new mechanism to create highly accelerated hot-carrier damage into FinFET devices by two-photon laser. This method is analogous to real use hot-carrier damage and offers an interesting alternative to understand the aging effects in VLSI circuits for high reliability applications.

Hot-Carrier Aging by Ultrafast Laser on 22FLL FinFET Technology

We report on charge capture and emission of Metal-Oxide-Semiconductor AlGaN/AlN/GaN High-Electron Mobility Transistors (MOSHEMT). Defects in HfO2 or AlO result in significant instabilities, with dielectric-dependent emission: band alignment between high-k shallow defect levels and AlGaN conduction band enables full (Al2O3) or partial (HfO2) charge de-trapping. These findings are significant as reliability modes under DC stress also contribute at RF operating conditions.

DC Reliability study of high-k GaN-on-Si MOSHEMTs for mm-Wave Power Amplifiers

Pioneer chip markets, such as data centers or the automotive industry, have a growing demand for dependable and secure chips to sustain power efficiency and long-term performance. The inevitable degradation of chip reliability caused by the two major aging mechanisms, BTI and HCD, may cause critical chip performance degradation. In this paper, we present our latest on-chip odometer technology, employed to accurately quantify in-field Si degradation using our two new designs of RO-based odometers.

Demonstration of Chip Overclock Detection by Employing Tamper-aware Odometer Technology

We performed a systematic study on HCI in I/O n/p-FinFETs. We extended our investigation to p-MOS with more process optimization techniques. We observed that HCI can be improved by higher S/D ext. implant dose/energy/tilt angle, smaller S/D CD, and larger proximity. We confirmed HCI improvement is attributed to the reduced lateral electric field in the drain due to the larger velocity saturation region. We summarized various strategies that can be used to optimize HCI reliability.

A Systematic Study of HCI Improvement in FinFET with Source/Drain Implant and Geometry Modulation

Quantum Computing has continued to gain traction in having the potential to shape the future of computing. In this talk, I will discuss some of the latest developments in the field - from a technical as well as business viewpoint. This presentation will also share engineering advancements and challenges, not only in the processors powering the quantum computer but the entire system. As we move on the path towards quantum advantage and broader commercialization of this technology, the focus on longer term reliability of the key components will become even more critical and aspects related to superconducting qubit-based quantum computers will be highlighted. Finally, a vision of where we see the inevitable convergence of high performance classical computers (HPC) with quantum computers, in what is termed as quantum-centric supercomputing will be presented.

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Fundamental understanding of NBTI degradation mechanism in IGZO channel devices

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Decoupling Current and Voltage Mediated Breakdown Mechanisms in CVD MoS2 FETs

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