United States

We report distinct breakdown mechanisms in CVD monolayer MoS2 FET devices for the first time mediated by either voltage or currents in devices. A detailed analysis of the breakdown physics explains the operational effects led shortcomings expected in downscaled devices. Operating short channel TMDs devices would be tricky owing to the dipole moment making it imperative to address the piezoelectric response related drifts in search of reliable performance.

IRPS 2024 Main Conference

Decoupling Current and Voltage Mediated Breakdown Mechanisms in CVD MoS2 FETs

2d tmd

voltage

current

breakdown

mos2

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

A robustness assessment has been performed for 77GHz power amplifier. First, a study performed at device level with RF stress illustrates the process capability to support HCI for aggressive mission profile, then secondly a robust setup OLT has been used to carry out 500h stress on several samples. The spread observed on degradation can be explained with Monte Carlo simulation of the complete TX chain. Adequation with ageing model are rather good.

Robustness assessment through 77GHz Operating Life Test of power amplifier for radar application in 28nm FD-SOI CMOS

This work reports a new mechanism to create highly accelerated hot-carrier damage into FinFET devices by two-photon laser. This method is analogous to real use hot-carrier damage and offers an interesting alternative to understand the aging effects in VLSI circuits for high reliability applications.

Hot-Carrier Aging by Ultrafast Laser on 22FLL FinFET Technology

In this paper, we examine the impact of recently introduced low thermal budget HKMG treatments on stress-induced leakage current and defect generation in pMOS devices. We also conduct time-dependent dielectric breakdown measurements to analyze Soft-Breakdown behavior and compare extrapolated lifetimes with conventional high-performance logic devices. Additionally, we explore the effects of a new low-temperature treatment that enhances the quality of the high-k (HK) layer to meet high-temperature  TDDB standards.

SILC and TDDB reliability of novel low thermal budget RMG gate stacks

We study oxygen flow role during IGZO PVD process on high temperature PBTI in back-gated TFTs by combining light-assisted with electrical stress measurements. Oxygen flow is observed to affect the magnitude of charge trapping and hydrogen related channel doping during PBTI. We show a correlation between sub-gap DOS and oxygen flow during deposition: the larger the oxygen flow, the smaller the light response at time-zero and its increase during PBTI, despite a larger negative DVth. 

Light-assisted investigation of the role of oxygen flow during IGZO deposition on deep subgap states and their evolution under PBTI

A full characterization of deep-level-effects in N-polar GaN-based-HEMTs has been carried out by means of Drain-Current-Transient-Spectroscopy (DCTS). The effect of ohmic-contacts, composition of AlGaN-cap-layer, and of the quality of the epitaxial layers have been studied. We show that the occurrence of the “antidispersion”  (ID transient increase during pulsed-measurements), due to negative-shift of threshold-voltage, is related to Fe-related-defects ionization. Through device and epitaxy optimization, dispersion-free devices, showing a 15% transient increase of drain current were obtained.

Deep level effects in N-polar AlGaN/GaN High Electron Mobility Transistors: towards zero dispersion effects

The lithium-ion battery experiences catastrophic failure as its health degrades rapidly (knee-point failure). The majority of prior models focus on estimating battery health during its usage phase. This study proposes a cell lifetime degradation model that addresses all three phases of battery life: calendar aging, cycle aging, and post-knee aging.  Experimental data has been used to build individual models for the three stages which have later been combined to form the cell lifetime degradation model. 

Cell Lifetime Degradation Model Development for Li-Ion Coin Cells considering Calendar Aging and Post-Knee Degradation

We performed a systematic study on HCI in I/O n/p-FinFETs. We extended our investigation to p-MOS with more process optimization techniques. We observed that HCI can be improved by higher S/D ext. implant dose/energy/tilt angle, smaller S/D CD, and larger proximity. We confirmed HCI improvement is attributed to the reduced lateral electric field in the drain due to the larger velocity saturation region. We summarized various strategies that can be used to optimize HCI reliability.

A Systematic Study of HCI Improvement in FinFET with Source/Drain Implant and Geometry Modulation

5G, Beyond 5G and 6G phased arrays for communications and sensing are being developed for consumer use. The communication system requirements lead to a few phased array architectures, package and semiconductor process options which then impact common reliability concerns and challenges. Integrated system and technology co-design offers opportunities for improvements in the handset and adjacent device spaces.

Reliability Considerations for 5G and 6G Phased Arrays

This paper presents transformer-based deep learning approach for outlier detection, reducing DPPM while maintaining competitive testing costs. Outlier ICs are identified by comparing deep learning-predicted parameters and corresponding measured values. Comparative analysis with D-PAT, NNR, and machine learning approaches validates our method's superior DPPM reduction: 62% compared to D-PAT, 13% compared to NNR, and 8% compared to machine learning method. Physical analysis confirms our method's sensitivity to latent defects, highlighting cost-effectiveness in achieving automotive-grade quality.

Utilizing Transformer Deep Learning Based Outlier Detection to Screen Out Reliability Weak ICs

Quantum Computing has continued to gain traction in having the potential to shape the future of computing. In this talk, I will discuss some of the latest developments in the field - from a technical as well as business viewpoint. This presentation will also share engineering advancements and challenges, not only in the processors powering the quantum computer but the entire system. As we move on the path towards quantum advantage and broader commercialization of this technology, the focus on longer term reliability of the key components will become even more critical and aspects related to superconducting qubit-based quantum computers will be highlighted. Finally, a vision of where we see the inevitable convergence of high performance classical computers (HPC) with quantum computers, in what is termed as quantum-centric supercomputing will be presented.

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Robustness assessment through 77GHz Operating Life Test of power amplifier for radar application in 28nm FD-SOI CMOS

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Next from IRPS 2024 Main Conference

Robustness assessment through 77GHz Operating Life Test of power amplifier for radar application in 28nm FD-SOI CMOS

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads