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This paper addresses the correct analysis of thick-oxide devices that mimic HV periphery devices of 3DNAND. Thick oxides grown close to the STI are found to be thinner at the edges. We introduce a model that divides the oxide into three different regions with different EOTs. This explains the conflicting electrical data and highlights the role of corners on leakage and breakdown. Applying the model to different oxide-growth processes provides guidelines to limit thickness variations.

IRPS 2024 Main Conference

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics

poster

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

DRAM reliability issues, including static data retention and tRDL, have proven challenging as interface trap density increases through scaling. Some ionic charges, such as chlorine and hydrogen, are inevitably in-flowed in DRAM cells during Trench Sidewall Silicon Oxide (Trench-Ox) process. These ionic charges not only serve as traps but also have negative impact on DRAM structure. In this paper, we propose a novel interface engineering of Trench-Ox that improves reliability and wiggled patterns of DRAM.

Interface Engineering of Trench-Ox for Modern DRAM Devices

Temperature affects performance, power and energy efficiency of system-on-chips (SOC). In this work, Monte Carlo (MC) calibrated device transport models are used to study thermal effects on block level PPA using imec's A14 technology. Self-heating raises the SOC operational temperature (T) as function of the power (P). At the same time, that power itself varies with temperature. An electrothermal model is used to account for this P-T interdependency and to obtain a final self-consistent solution.

Thermal Performance Evaluation of Multi-core SOCs Using Power-Thermal (P-T) Co-simulation

High-energy X-rays are used in PCB inspection systems to ensure electrical connectivity between components. The X-rays used in these systems often have energy ranging from a few keV to 150 keV. Exposure to these X-rays can cause a shift in individual transistor parameters due to total-ionizing dose (TID) effects. This damage is characterized for commercial PCB inspection systems along with mitigation techniques.

Total-Ionizing Dose Damage from X-Ray PCB Inspection Systems

We propose a radiation-hardened FF combined with a transient-fault tolerant (TFT) structure and fabricated test chips in a 65 nm FD-SOI technology. Experimental results show that the soft error rate of the proposed TFT FF is three orders of magnitude lower than that of a standard FF. The TFT FF has 35% area, 15% delay and 9% power overhead, and its energy-delay product is half as large as a conventional stacked FF.

A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead

Single event cross section trends are investigated at near-threshold-voltage (NTV) supply voltages for different VT options and RHBD flip flop designs at the 5-nm bulk FinFET node. Results show very different responses for each design yielding a wide range of choices for meeting design specifications.

Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages

We propose an SER evaluation method for terrestrial applications using a clinical carbon beam facility. We compared the results of the proposed method with those of white neutron irradiation using flip-flops in a 65 nm bulk process. The SERs evaluated by our method are strongly correlated with those by white neutron irradiation, and the difference in both SERs is approximately 25%. Clinical carbon beam facilities can be use as alternative facilities for SER evaluation. 

An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/u Carbon Beam and Particle Transport Simulations

This paper presents a single event upset (SEU) cross section model reproducing the linear energy transfer (LET) and the voltage dependence in the bulk planar and FinFET static random-access memories (SRAMs). The model predicts both the LET and the applied voltage (VDD) dependence with physically explainable parameters.

An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs

Image recognition was performed on members of the MNIST and FashionMNIST datasets on two different MCUs while exposing them to a neutron beam. Four types of application-level effects were observed, with some or all effects in each category resulting in application hangs or misclassifications of the test images. Three effects manifest continuously until the core is reset. The data also suggests that image complexity has a positive association with the number of application-level errors expected.

Soft Error Induced System Errors in Image Inference Applications with Glow-Compiled CNNs on MCUs

Multiple bit upsets (MBUs) are observed in shift register circuits at the 5-nm bulk FinFET node for alpha particles and heavy ions.

Multiple Bit Upsets in Register Circuits at the 5-nm bulk FinFET node

This paper introduces an essential on-chip architecture to characterize Random Telegraph Noise (RTN) accurately for modern integrated circuits (ICs), demonstrated through results from test structures in SkyWater Technology's 90 nm CMOS process. A comprehensive multi-step process, including a pre-processing scan of a 96x128 device array, offers insights into device variability and RTN, guiding more efficient CMOS design strategies.

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Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics

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Interface Engineering of Trench-Ox for Modern DRAM Devices

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