United States

A novel vertical channel DRAM cell array transistor has been proposed and verified. A back gate shared by adjacent two word lines has been introduced to have both word line disturb immunity and threshold voltage controllability, while having a small foot print and corresponding scalability. The increased word line coupling has less effect on overall word line disturb immunity, by virtue of insignificant passing gate effects and reduced variability.

IRPS 2024 Main Conference

Effect of Back Gate on Word Line Disturb Immunity of a Vertical Channel DRAM Cell Array Transistor

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#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Cross temperature effect is a fundamental reliability concern for 3D NAND Flash memory. In this paper we explore the origin of cross temperature reliability by measuring the cell threshold voltage (Vth) distribution at different temperatures. We observe significant cell-to-cell variability in the temperature coefficients causing distribution widening. We provide a conceptual picture to model the distribution widening based on sub-threshold slope factor variation. We also discuss two system level countermeasures to minimize the cross-temperature effects.

Cross-Temperature Reliability of 3D NAND: Cell-to-Cell Variability Analysis and Countermeasure

In this work we develop a retention model of 3D NAND and: (1) show importance of the blocking oxide quality improvement and lateral migration suppression (through alternative integration schemes) as a key retention enhancer; and (2) develop a superior SiO2 with low defectivity and demonstrate a direct relationship between blocking oxide, SiO2 defectivity and data loss during retention.

Blocking oxide material engineering to improve retention loss in 3D NAND: a modeling process optimization study

In this work, we evaluate the scaling limits of inter-word line dielectrics for 3D NAND Flash devices. We test different oxide stacks by mimicking the stacked architecture using planar capacitors. We conclude that a ~17% reduction in stack height, from 24 nm to 20 nm, can be obtained by removing the High-K liner from the top and bottom of the SiO2, without compromising device reliability.

P27.MR -Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND

Two oxidation methods to optimize the BE SiON. Molecular-mode oxidation operates in a diffusion-based manner, leading to deeper oxidation throughout the entire SiON. In contrast, radical-mode oxidation, classified as an exchange-mode process, primarily targets the SiON surface. Using our 3D AND-type NOR Flash memory, both molecular and radical oxidation techniques were applied to the BE-MANOS device for chip-level reliability study. Both molecular and radical oxidation shows obvious improvements (15-25%) on post-cycled retention performances.

Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide

We investigated the RowPress (RP) effect for sub-20 nm DRAM. Single- and double-sided RP are compared with row hammer (RH). Distinct RP leakage mechanisms are identified, illuminating its different cell vulnerability in contrast to RH. AWL-induced RP results in 0 failure, whereas PWL-induced RP leads to 1 failure, demonstrating different bit-flip directionality from RH. Mechanisms behind the differences in the dependences on temperature and access pattern between RH and RP are analyzed.

Understanding the Physical Mechanism of RowPress at the Device-Level in Sub-20 nm DRAM

In this work, an efficient multi-link EM pattern was proposed to understand fabrication defects and low-percentile EM reliability modeling. Without collecting over thousand samples, proposed multi-link EM patterns successfully validated lognormal based 3-parameter at &lt;1% lifetime extrapolation based on weakest link statistics. Released EM lifetime and higher current density with efficient test time demonstrated the importance of accurate low-percentile EM reliability model by multi-link structure to enable transistor scaling in back-end-of-line process innovations.

Enhancing EM Reliability and Lifetime Modeling: A Multi-link Structure Approach

Electronic devices increasing complexity and reduced material redundancies raise concerns about physical failures, especially in metal interconnects. Among various mechanisms, thermomechanical-induced damage, initiated by short bursts of current, remains a major reliability challenge. Experimental and numerical investigations were conducted on Al-SiO2 structure, revealing distinct failure behaviors based on power input and interconnect dimensions. The findings highlight the danger of surge current-driven damage and the need for careful analysis and mitigation strategies in advanced packaging design.

Study of Thermomechanical Damage Mechanism in Al Interconnects in Al-SiO2 structure by High Density Peak current

Using a W-line with Cu injectors, we analyzed the impact of thermal gradients on Cu interconnects lifetime. Self-heating was experimentally assessed, and Cu temperature was estimated through an electro-thermal model. Experimentally, we find a low EM-EA~0.8eV, suggesting other failure mechanisms. Our 1D physics-based model predicts 3x faster void nucleation for EM+TM and a corrected EA~0.89eV, closer to the measured EM-EA. This finding allows a more reliable lifetime estimation under operating conditions with high thermal gradients.

De-coupling Thermo-migration from Electromigration using a dedicated test structure

Impacts of BEOL queue time (Q-Time) from post-Cu CMP (Chemical Mechanical Polish) to SiCN capping layer on reliability were investigated. Degradation in electromigration (EM) was observed in both Cu/Low-k (LK) and Cu/Ultra-low-k (ULK) interconnects due to Cu surface oxidation. However, there is no reliability impact in LK dielectric, while significant degradation in ULK dielectric. EM degradation in long CMP Q-Time could be recovered by CMP Buff process.

Impacts of Post-Cu CMP Queue Time on Reliability

In this work, we explored the self-heating effect (SHE) and performance analysis of Backside Power Delivery Network (BSPDN) technology for routing logical signals from underlying devices to SRAM macros and 3nm technology nodes. A comprehensive evaluation was conducted on the impact of using BSPDN on the thermal effects and performance of circuits in terms of Power, Performance, Area, and Thermal (PPAT) from devices to circuits.

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Effect of Back Gate on Word Line Disturb Immunity of a Vertical Channel DRAM Cell Array Transistor

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Cross-Temperature Reliability of 3D NAND: Cell-to-Cell Variability Analysis and Countermeasure

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