United States

Temporal characteristics of O2-doped MoS2 (MoS2:O)-based Ru/MoS2:O/Pt RRAM demonstrate that, basal-plane oxidation of MoS2 during its sputter-deposition in optimized O2 protects RRAM from environment. Mo3d (XPS) from 3-months’ MoS2:O revealed lesser Mo+6 (edge; MoO3)-to-Mo+4 (basal; Mo-O) ratio in MoS2:O than its un-doped counterpart, showing significant edge-oxidation (MoO3) in latter that adversely impacted monthly retention of RRAM having un-doped MoS2 film.

IRPS 2024 Main Conference

Impact of Edge and Basal Plane Oxidation on the Stability of Oxygen Doped MoS2-RRAM

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#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Hafnium zirconium oxide (HZO) doesn't meet endurance requirements for certain applications such as data logging. We introduce aluminum-doped HZO (HZAO)-based metal-ferroelectric-metal (MFM) capacitors integrated in BEoL to improve endurance characteristics. Wake-up characteristics, 2Pr and 2Ec are studied. Based on measurements under severe conditions, endurance was extrapolated with respect to electric field, temperature, frequency, and MFM area. Outstandingly enhanced endurance of above 1015 cycles are predicted. This enables usage of ferroelectric memories for data logging applications.

Improved endurance reliability of ferroelectric hafnium oxide-based BEoL integrated MFM capacitors

We investigate a drain current degradation in Fe-FET. This phenomenon is due to trapping/de-trapping charge rather than charged remnant polarization of ferroelectric layer. That is explained as a de-trapped compensation charge from the channel-side interfacial layer, and a trapped charge from substrate silicon channel. This modeling is confirmed by experimental and simulation results. Based on the thorough investigation, we propose pulse conditions for proper read operation and recommend physical parameters of channel IL in Fe-FET.

Drain Current Degradation Induced by Charge Trapping/De-trapping in Fe-FET

Ferroelectric field effect transistor can be read-out in a capacitive manner for improved energy efficiency, namely nvCAP mode. The reliability aspects such as endurance, retention and multi-level cell of nvCAP are evaluated. Impact of defect generation and charge-trapping on the endurance and retention behavior of nvCAP is investigated. The device sustains up to 107 program-erase cycles until the Con/Coff ratio becomes ~1. A C-V sweep performed on the fatigued device ‘recover’ the performance.

Reliability Assessment of Ferroelectric nvCAP for Small-signal Capacitive Read-out

We investigate the mechanism of time-dependent degradation of MgO barrier and propose a way to suppress it. Resistance drift and degradation in tunnel magnetoresistance ratio under an operating voltage were experimentally observed in scaled MTJs. With microscopic calculations, we find that the degradation can be explained by current-induced generation of oxygen Frenkel defects at the interface of MgO and Fe. We reveal that the reduction of initial oxygen vacancies in MgO can suppress the degradation.

Microscopic modeling of MgO barrier degradation due to interface oxygen Frenkel defects in scaled MTJ toward high-density STT-MRAM

Physics of experimentally observed abnormal behavior in STI bounded Silicon-Controlled-Rectifier (SCR) structures is investigated and explained using basic principles and 3D electrothermal TCAD simulations. The SCR device is found to show pulse to pulse instability in the snapback region during 100ns pulse width TLP measurement. The instabilities depended on the load line conditions used in the TLP measurement. The physical insights and device physics has been explored using well calibrated 3D process and device TCAD.

Loadline Dependent Current Filament Dynamics in Nanoscale SCR Devices

Anti-ferroelectric HfZrO thin films exhibit favorable properties for advanced embedded DRAM. However, their failure mechanisms have not been well-understood. In this work, it was confirmed that the orthorhombic-I phase is directly attributed to the AFE characteristics. Moreover, around the thickness of 6 nm, a reversible transition between the orthorhombic-I  and tetragonal phases occurs, enhancing the stability of the AFE properties. Furthermore, a record-high measured endurance of 1014 has been experimentally demonstrated for the first time.

Orthorhombic-I Phase and Related Phase Transitions: Mechanism of Superior Endurance (&gt;10^14) of HfZrO Anti-ferroelectrics for DRAM Applications

Phase change memory (PCM) is one of the most promising technologies for embedded nonvolatile memory because of high scalability and high-temperature data retention with Ge-rich GeSbTe. Ge-rich GST is affected by drift on both set and reset states which limits the stability of a multilevel cell and the accuracy of in-memory computing. This work presents a new methodology for precise, drift-stable MLC programming based on the weak reset operation to initialize the PCM device.

Drift compensation in multilevel PCM for in-memory computing accelerators

In this work co-optimization of Silicon controlled rectifier (SCR) ESD characteristics with its low voltage trigger circuit is presented.  The low trigger circuit design approach is discussed and presented. In the process we find that some of the trigger circuits previously reported in literature do not work as desired until co-optimization device engineering techniques are used. The circuit insights are explored using well calibrated electrothermal 3D process and device TCAD mixed mode simulations.

Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR

Devices used in space detection may operate at 600 K, so latches can occur in extreme environments. Through experiments and TCAD simulation, the leakage current mechanism is analyzed in this paper. The proposed analytical model can perfectly predict the latch-up voltage. Both self-heating and leakage current can be suppressed using the back gate bias, which also increase 1/f noise. The influence mechanism of the back gate was verified through TCAD.

Research on the Latch-up Mechanism of DSOI at High Temperature

The integrated circuits must be verified through latch-up test, according to the JESD78F.01 standard. This work presented a specific latch-up challenge encountered in an IC product, where a multi-functional I/O buffer suffered latch-up failure, due to the indirect connection on the N-well of output PMOS to the power supply through a bias switch. By using an embedded deep-nwell collector, the latch-up immunity of such a multi-functional I/O buffer can be significantly improved.

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Impact of Edge and Basal Plane Oxidation on the Stability of Oxygen Doped MoS2-RRAM

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Improved endurance reliability of ferroelectric hafnium oxide-based BEoL integrated MFM capacitors

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