United States

This works presents a 5-V tolerant supply clamp for ESD protection in 16nm FinFET technology. Active feedback is employed to enable a very small RC time constant (4 ns) used in the timer circuit. The small RC time constant makes the clamp robust to unwanted triggering during fast power ramp-up, while the feedback circuit sustains the clamp on for the entire duration of a 2-kV HBM event.

IRPS 2024 Main Conference

Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology

supply clamp

finfet

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

On-chip sensors are a key tool in characterizing wear-out processes in semiconductors. We present a novel sensor design that can separably monitor transistor wear-out under BTI and HCI stress regimes in both NMOS and PMOS transistors and that allows for DC read-out. The design is implemented in a 12nm FinFET process and subjected to 1500 hours of stress to verify the sensor and provide insights into scaled CMOS degradation behaviours.

A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process

In this paper, we have monitored the cycle-to-cycle variation (CCV) of ultra-scaled FinFETs during HCD and BTI stress. Different measurement speeds have been utilized to separate the intrinsic CCV from the stress-induced CCV. Statistical of nFinFETs shows under the same amount of ΔVth, PBTI induces a larger dynamic variability than HCD. Surprisingly, pFinFETs with under much Vth degradation show only a little Vth variation, suggesting its less sensitivity to stress-induced CCV.

Impact of Hot Carrier Degradation and Bias Temperature Instability on GHz Cycle-to-cycle Variation in Ultra-scaled FinFETs

During CDM ESD events, MOSFET gate oxides may be exposed to high voltage stress for a few hundred picoseconds, and the gate oxide breakdown voltage is important for ESD designers. This work presents an on-chip pulse generator capable of producing clean pulses with amplitude up to 6 V and pulse width as short as 200 ps. The pulse generator is used for an experimental investigation of gate oxide breakdown voltage on a sub‑ns timescale.

On-Chip Single-Shot Pulse Generator for TDDB Characterization on a Sub-nanosecond Timescale

We successfully developed a statistics-based model, specifically the joint Weibull-Fréchet model, with only four parameters to characterize reverse area-scaling of tBD data in good agreement. This model can be used to subsequently extract parameters in defect generation-annihilation processes implemented in the physics-based model. More importantly, this model can be used for reliability projection from test areas to the ultimate chip area.

General statistical model for dielectric breakdown including reverse area scaling – The role of area-dependent dynamic competition

This paper studies on NBTI starting with 100 ns in DRAM for the first time. Ultra-fast e-traps were isolated by advanced CP. Distinct types of slow traps were separated using DMP. Considering NMP theory, we precisely obtained spatial and energy distribution of various traps and, through comparison with ab-initio calculations, revealed that these traps originate from nitrogen substitution, oxygen vacancies, and nitrogen interstitial. The results contribute to understanding of the reliability of DRAM.

DRAM Technology under Negative Bias Temperature Instability (NBTI) : from Characterization to Physical Origin Identification

In this paper, a thermal analysis of a server SoC is performed, considering a realistic layer stack configuration mounted on a printed circuit board (PCB) with an active heat sink for the cooling solution. We investigated the impact of the heterogeneous power distribution within the SoC cluster. This paper also reports the thermal transients with workload conditions, which lead to improvement in thermal reliability and performance by ~26% of the proposed A10 node server SoC.

Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies

In this work the impact of cryogenic temperatures on latchup in 28 nm planar bulk CMOS technology is discussed. Measurement and simulation results indicate that at low temperatures the wells sheet resistances increase more that 50% which can lead to increased latchup risk. However, our results show that the current gain product of the parasitic bipolar transistors reduces with cryogenic temperatures that can compensate LU risk.

Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications

We developed ALD InGaOx (IGO) and InSnOx deposition process for channel and electrode, respectively. We systematically investigated the relationship among mobility, electrostatics, and reliability by studying composition and thickness dependence, and confirmed clear trade-off in IGO FETs. To break this trade-off, we designed and fabricated double-gate nanosheet IGO FETs demonstrating normally-off operation, high mobility and high reliability, simultaneously.This work provides a practical device design guide for developing ALD-based oxide semiconductor FET for 3D integrated devices.

Performance and reliability of nanosheet oxide semiconductor FETs with ALD-grown InGaO for 3D integration

Ferroelectricity boosted gate stacks, such as dual ferroelectric layer and charge trap layer (dual FE-CTL), have been proposed. In this work, interface defect generation and degradation of short time data retention due to cycling on dual FE-CTL devices are investigated by fast I-V measurement. The results reveal significant advantages in  reliability. In addition, lower transient gate current during program is observed, which can explain the root cause of the improvements on dual FE-CTL gate stacks.

Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance

In this paper, we propose some layout guidelines to significantly mitigate the charging damage from well-side antennas in separated power domains. The circuit topologies that consist of aggressor-victim pairs. The guidelines are based on the test patterns that cover adequate combinations of different geometries of isolation wells, metals, and vias, as well as different well configurations. The method has been verified in 0.13µm BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer) as the isolation well.

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Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology

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A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process

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