United States

On-chip sensors are a key tool in characterizing wear-out processes in semiconductors. We present a novel sensor design that can separably monitor transistor wear-out under BTI and HCI stress regimes in both NMOS and PMOS transistors and that allows for DC read-out. The design is implemented in a 12nm FinFET process and subjected to 1500 hours of stress to verify the sensor and provide insights into scaled CMOS degradation behaviours.

IRPS 2024 Main Conference

A Novel Induced Offset Voltage Sensor for Separable Wear-Out Mechanism Characterization in a 12nm FinFET Process

semiconductor device breakdown

analog circuits

accelerated aging

integrated circuit reliability

sensors

We are pleased to announce the Fortieth AAAI Conference on Artificial Intelligence (AAAI-26), which will be held in Singapore EXPO from January 20 to January 27, 2026.

The purpose of the AAAI conference series is to promote research in Artificial Intelligence (AI) and foster scientific exchange between researchers, practitioners, scientists, students, and engineers across the entirety of AI and its affiliated disciplines. AAAI-26 will feature technical paper presentations, special tracks, invited speakers, workshops, tutorials, poster sessions, senior member presentations, competitions, and exhibit programs, and a range of other activities to be announced.

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AAAI 2026

We are pleased to announce the Fortieth AAAI Conference on Artificial Intelligence (AAAI-26), which will be held in Singapore EXPO from January 20 to January 27, 2026.

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

We successfully developed a statistics-based model, specifically the joint Weibull-Fréchet model, with only four parameters to characterize reverse area-scaling of tBD data in good agreement. This model can be used to subsequently extract parameters in defect generation-annihilation processes implemented in the physics-based model. More importantly, this model can be used for reliability projection from test areas to the ultimate chip area.

General statistical model for dielectric breakdown including reverse area scaling – The role of area-dependent dynamic competition

In this work, we introduce a physics-informed machine learning framework that can build a model of stochastically behaving defects in the gate oxide of an individual scaled transistor device. This is achieved by automated data-driven analysis of low-voltage stress-induced leakage current data constituting convoluted random telegraph noise signals. The decision-making of the framework is guided by defect physics. Furthermore, it was successfully applied to generate statistics on defect properties in multiple devices.

Physics-informed machine learning to analyze oxide defect-induced RTN in gate leakage current

This paper studies on NBTI starting with 100 ns in DRAM for the first time. Ultra-fast e-traps were isolated by advanced CP. Distinct types of slow traps were separated using DMP. Considering NMP theory, we precisely obtained spatial and energy distribution of various traps and, through comparison with ab-initio calculations, revealed that these traps originate from nitrogen substitution, oxygen vacancies, and nitrogen interstitial. The results contribute to understanding of the reliability of DRAM.

DRAM Technology under Negative Bias Temperature Instability (NBTI) : from Characterization to Physical Origin Identification

Long Read-After-Write-Delay (RAWD) is one of the Show stoppers (S.S) in ferroelectric based VNAND (Fe-VNAND) because of limited read speed. We investigated the RAWD time (tRAWD) in MFIS as well as Laminate-MFIS  (LaMFIS). In LaMFIS, Vt tends to increase slightly at low voltage during Incremental Step Positive Pulse (ISPP) operation. This is caused by the accumulation of trapped electrons at the inserted layer. The novel ISPP scheme removed these electrons and therefore improved device performance.

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

We present an experimental investigation that relates the TDDB dynamics in polymeric dielectrics for galvanic isolators to the moisture content in the material. By looking at the temperature dependence of TDDB, we provide a clear explanation for the impact of moisture on the activation energy of device lifetime and support our picture quantitatively with a physics-based model. Results point out primary aspects to consider when assessing the reliability of galvanic isolators based on polymeric dielectrics.

Investigation of the Moisture-Driven Dynamics of Time-Dependent Dielectric Breakdown in Polymeric Dielectrics for Galvanic Isolators

Due to the demands of AI and HPC, HBM is becoming more high-capacity with multi-die stacks and more complex internal structures. As the number of HBM in SiP also increases, reliability of HBM on SiP has become significant. The main purpose of this study is to compare the structure and stresses of each DUT based on FEA and to analyze the reliability characteristics of HBM by simulating SiP.

Thermo-Mechanical Reliability Characteristics of HBM3

In this work the impact of cryogenic temperatures on latchup in 28 nm planar bulk CMOS technology is discussed. Measurement and simulation results indicate that at low temperatures the wells sheet resistances increase more that 50% which can lead to increased latchup risk. However, our results show that the current gain product of the parasitic bipolar transistors reduces with cryogenic temperatures that can compensate LU risk.

Insight into Latchup Risk in 28nm Planar Bulk Technology for Quantum Computing Applications

We developed ALD InGaOx (IGO) and InSnOx deposition process for channel and electrode, respectively. We systematically investigated the relationship among mobility, electrostatics, and reliability by studying composition and thickness dependence, and confirmed clear trade-off in IGO FETs. To break this trade-off, we designed and fabricated double-gate nanosheet IGO FETs demonstrating normally-off operation, high mobility and high reliability, simultaneously.This work provides a practical device design guide for developing ALD-based oxide semiconductor FET for 3D integrated devices.

Performance and reliability of nanosheet oxide semiconductor FETs with ALD-grown InGaO for 3D integration

Ferroelectricity boosted gate stacks, such as dual ferroelectric layer and charge trap layer (dual FE-CTL), have been proposed. In this work, interface defect generation and degradation of short time data retention due to cycling on dual FE-CTL devices are investigated by fast I-V measurement. The results reveal significant advantages in  reliability. In addition, lower transient gate current during program is observed, which can explain the root cause of the improvements on dual FE-CTL gate stacks.

Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance

In this paper, we propose some layout guidelines to significantly mitigate the charging damage from well-side antennas in separated power domains. The circuit topologies that consist of aggressor-victim pairs. The guidelines are based on the test patterns that cover adequate combinations of different geometries of isolation wells, metals, and vias, as well as different well configurations. The method has been verified in 0.13µm BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer) as the isolation well.

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General statistical model for dielectric breakdown including reverse area scaling – The role of area-dependent dynamic competition

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