United States

Deep neural networks (DNNs) have gained widespread applications in numerous applications, especially for embedded and Internet-of-Things (IoT) devices. Nowadays on-device DNN inference has been extensively investigated because of its inherent advantages on data privacy, response time and bandwidth demand than cloud-based inference. On the other side, on-device DNN learning, which also has very strong practical demands and owns the similar advantages over the cloud-based training, however, has not been widely studied yet due to the dilemma between expensive training cost and limited on-device resource.  To address this challenge and promote the further deployment of on-device learning, this project proposes to leverage low-rank tensors, as a powerful mathematical tool for representing and compressing tensor-format data, to achieve real-time energy-efficient DNN learning on the device. 

https://underline.io/speakers/59507-bo-yuan

NSF Workshop on Micro/Nano Circuits and Systems Design

TensorNN: An Algorithm and Hardware Co-design Framework for On-device Deep Neural Network Learning using Low-rank Tensors

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

ESSCIRC ESSDERC Educational Events

The Educational Events of ESSCIRC ESSDERC 2021. 

poster

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


Machine learning is the key to sustaining the economic growth in many sectors within the U.S. science and engineering enterprise. Neuromorphic architectures that mimic biological neurons and synapses can execute machine learning algorithms in an energy-efficient manner, allowing for their integration with the internet-of-things, another industry sector projected to have an economic impact of more than $1 trillion by 2025. However, neuromorphic architectures are fundamentally unreliable. They introduce errors during execution, limiting the dependability of machine learning and impeding their technological progress. This project will address dependability challenges of neuromorphic computing, by looking at all levels, from building error-resilient machine learning algorithms to designing fault-tolerant hardware. This project will advance the field by 1) making neuromorphic computing reliable, efficient, programmable, and easy-to-use for the community, 2) teaching future science and engineering students how to make machine learning algorithms error-resilient, 3) creating job opportunities in neuromorphic industry through national and international internships and collaborations, 4) raising interest of high school students in STEM through neuromorphic computing enabled robotics workshops, and 5) building an integrated neuromorphic community through a new focused conference on neuromorphic computing.

https://underline.io/speakers/59508-anup-das

Facilitating Dependable Neuromorphic Computing: Vision, Architecture, and Impact on Programmability

We present and investigate a novel application domain for deep reinforcement learning (RL): droplet routing on digital microfluidic biochips (DMFBs). A DMFB, composed of a two dimensional electrode array, manipulates discrete fluid droplets to automatically execute biochemical protocols such as point-of-care clinical diagnosis. However, a major concern associated with the use of DMFBs is that electrodes in a biochip can degrade over time. Droplet-transportation operations
associated with the degraded electrodes can fail, thereby compromising the integrity of the bioassay outcome. We show that casting droplet transportation as an RL problem enables the training of deep network policies to capture the underlying
health conditions of electrodes and provide reliable fluidic operations. We propose a new RL-based droplet-routing flow that can be used for various sizes of DMFBs, and demonstrate reliable execution of an epigenetic bioassay with the RL droplet router on a fabricated DMFB. To facilitate further research, we also present a simulation environment based on the OpenAI Gym Interface for RL-guided droplet-routing problems on DMFBs.

https://underline.io/speakers/60045-krishnendu-chakrabarty

Adaptive Droplet Routing in Digital Microfluidic Biochips Using Deep Reinforcement Learning

Emulating the cognitive abilities of the brain will enable new paradigms in computing not currently accessible with digital architectures. This poster discusses the use of CMOS circuits in conjunction with devices such as resistive memory (memristors) that mimic the complex synaptic learning modalities found in the brain. System level time-dynamics is examined in the context of spatio-temporal pattern recognition. This research will ultimately advance the capabilities of intelligent computers for sensory processing and control, anomaly detection, and inference and outcome prediction.

https://underline.io/speakers/59511-kurtis-cantley

Spiking Neural Circuits for Temporally Dynamic Learning

This presentation covers the overview of our NSF medium project and reports on the recent progress including novel deep neural network pruning and quantization methods recently published.

	https://underline.io/speakers/55839-xue-lin

A Unified Software/Hardware Framework of DNN Computation and Storage Reduction Using ADMM

This poster presents a technique to leverage artificial intelligence (AI) to reduce energy transmission in image sensor networks. A multi-task learning analog AI circuit will be embedded in CMOS image sensor to 1) identify relevant frames for transmission; and  2) perform image compression before transmission. Initial measurements results in 65nm process are demonstrated on low-resolution MNIST dataset. The analog AI classifier achieves state-of-the-art energy efficiency.

https://underline.io/speakers/59512-arindam-sanyal

On-chip Multi-Task Learning Analog Artificial Intelligence For Low-Cost Image-Based Environmental Monitoring

I reviewed this NSF CAREER project on deep neural network acceleration using crossbar arrays with resistive random access memory (RRAM). The research accomplishments include several generations of the silicon prototypes including small-scale crossbar array for convolutional kernel (with integrated oscillation neuron), and two generations of compute-in-memory macro with peripheral analog-to-digital converters taped-out in Winbond 90nm RRAM and TSMC 40nm RRAM processes. Another research outcome is the NeuroSim benchmark framework which is an end-to-end simulator to evaluate the deep neural network training/inference accuracy under non-ideal synaptic device properties and to estimate the cycle-accurate and trace-enabled hardware performance including the chip area and energy/latency. I also surveyed future research directions: 1) 3D integration with hybrid technology nodes; 2) ferroelectric transistor as synaptic device; 3) security issues with compute-in-memory. 

https://underline.io/speakers/59513-shimeng--yu

CAREER: Scaling-up Resistive Synaptic Arrays for Neuro-inspired Computing

Information technology has entered the age of heterogeneous computing.  Across a variety of application domains, computing systems rely on highly heterogeneous architectures that combine multiple general-purpose processors with specialized hardware accelerators.  The complexity of these systems, however, threatens to widen the gap between the capabilities provided by semiconductor technologies and the productivity of computer engineers. Embedded Scalable Platforms (ESP) is a new approach to the design and programming of heterogeneous computing systems that raises the level of abstraction in the design process. ESP is an open-source research platform for heterogeneous SoC design that combines a scalable tile-based architecture and a flexible system-level design methodology. Conceived as a heterogeneous integration platform and tested through years of teaching at Columbia University, ESP is naturally suited to foster collaborative engineering of SoC designs across the open-source community.

https://underline.io/speakers/59514-luca-carloni


ESP: The Open-Source System-on-Chip Platform for Heterogeneous Computing

This talk firstly explains why we need to rethink design automation from a hybrid model-based and data-driven perspective, and why we need to extend EDA to multiple engineering domains.  Then I will introduce an uncertainty-aware data-driven design automation framework that can be applied to multiple engineering domains, and explain the shared theoretical challenges. Finally, I will highlight some of our recent theoretical results and demonstrate the applications in electronic IC, photonic IC, autonomous systems and AI systems. 

https://underline.io/speakers/59515-zheng-zhang

Uncertainty-Aware and Data-Driven Design Automation Techniques with Multi-Domain Applications

In recent days, 2.5D package designs have gained popularity with an increasing number of heterogeneous chiplets integrated into advanced system-in-packages. RDL wires become longer and denser, presenting a growing impact on system performance, reliability, and integrity. At present, there exists no standard CAD flow that can design, analyze, and optimize a complete heterogeneous 2.5D system. The traditional die-by-die design approach processes each component independently during extraction and optimization and cannot be applied to heterogeneous systems without fundamental changes in standard CAD tools. Not only the chiplet-package extraction is inaccurate between the die-package interface ignoring all RDL capacitive and inductive impacts, but traditional CAD tools are also unable to perform cross-boundary design optimization. 
We present a complete chiplet-package co-optimization flow for both homogeneous and heterogeneous 2.5D designs. It encompasses 2.5D-aware partitioning, chiplet-package co-planning, holistic and in-context extraction, package inductance consideration, and iterative optimization, along with design analysis and verification of the entire 2.5D system. For homogeneous 2.5D packages, the performance gap to the reference 2D design reduces by 62.5% with our holistic flow. Targeting heterogeneous systems, our in-context design flow achieves less than 1% extraction error on ground and coupling capacitance with comparable design performance.  We further validated our design flow with a design tape-out in TSMC 65nm.

https://underline.io/speakers/59516-yarui-peng

Design, Extraction, and Optimization of Multi-Chip Fan-Out Wafer-Level-Packaging for Low-Power Heterogeneous Systems

The goal of this project is to study the multiphysics, multilevel, multiscale stack of modeling, analysis and optimization from on-chip timing to system reliability under thermal cycling, and develop tools to support system analysis and optimization across this stack. Several recent highlights are presented in the poster.

https://underline.io/speakers/59611-andrew-kahng

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