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Enabling the efficient processing of deep neural networks (DNNs) has becoming increasingly important to enable the deployment of DNNs on a wide range of platforms, for a wide range of applications. To address this need, there has been a significant amount of work in recent years on designing DNN accelerators and developing approaches for efficient DNN processing that spans the computer vision, machine learning, and hardware/systems architecture communities. Given the volume of work, it would not be feasible to cover them all in a single talk. Instead, this talk will focus on *how* to evaluate these different approaches, which include the design of DNN accelerators and DNN models. It will also highlight the key metrics that should be measured and compared and present tools that can assist in the evaluation.

ESSCIRC ESSDERC Educational Events

How to Evaluate Efficient Deep Neural Network Approaches

accelerators

in-memory computing

deep neural networks

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

Three key challenges in the design of modern closed-loop neurostimulators for the treatment of neurological disorders, such as intractable epilepsy, are discussed. The first challenge is the need for the best possible efficacy by implementing neuromodulation therapies that are custom-tailored for each patient. Here, the question of where to employ machine learning, whether within the medical device or remotely is addressed, with two energy-efficient implementation examples given: a long-effective-memory SVM and a spatiotemporal CNN. The second challenge is a clear patients’ preference for lower invasiveness – two methods are presented that enable selective recruitment of nerves by decomposing the stimulus signal as it is being delivered to the target. This allows to break the trade-off between invasiveness and selectivity, but requires complex stimulation waveforms applied concurrently with the neural activity recording. As a result, the third challenge is the need for tolerance to stimulation artifacts. Delta-sigma quantization techniques to track fast input transients, by adapting DAC step size, ADC reference voltage and ADC clock frequency, are presented to address this challenge.

Artificially-intelligent Closed-loop Neurostimulators for the Treatment of Neurological Disorders

In this talk, we present emerging technologies for implantable CMOS optoelectronics for interfacing to the brain.

Implantable Optoelectronics for Neural Interfaces

Commercial 5G services have been launched globally. Study and development for technologies toward the evolution of 5G are ongoing, taking into account issues in early 5G services and emerging market needs. In parallel, research focused on technologies and services beyond 5G and 6G is accelerating throughout the world. This presentation will explain NTT DOCOMO's views and our latest activities on 5G evolution and 6G.

5G evolution and 6G: benefits and challenges

In this presentation, background and motivation will be explained for mmW/THz wireless communication as well as basics of phased-array theory. The theoretical limitation and possible direction of mmW/THz wireless communication is discussed with a THz phased-array transceiver implemented by 65nm CMOS.


Millimeter-wave/THz Phased-Array Transceiver for Beyond 5G

There is a rapidly increasing interest in beyond-5G and 6G wireless networks for the next-generation communication and sensing platform. It is envisioned that the upper mm-Wave and sub-THz frequencies (e.g. 100GHz to 240GHz) spectrum will be the major spectrum of interest due their abundant available bandwidth (BW) to achieve the “holy grail” of 1Tb/s wireless network throughput. It is also expected that large-scale arrays with massive elements will be a necessity and ubiquitously to provide huge array gains and compensate for the high-frequency path loss.
However, a major challenge at the physical layer for these beyond-5G and 6G networks is the lack of energy-efficient, wideband, and ultra-compact frontend electronics, in particular power amplifiers, at high mm-Wave/sub-THz. This is even more problematic for large-scale densely-packed arrays, where thermal management becomes a severe issue. Further, next-generation wireless links demand ultra-wideband modulations and high efficiency, while radar/imaging/sensing systems require large instantaneous BW. Despite of decades of research on integrated power amplifiers, most of these efforts have focused on RF and mm-Wave PAs, while high mm-Wave/sub-THz PAs entail distinct challenges at both device and circuit levels. In this talk, we will review the current state of the art of the high mm-Wave and sub-THz frequencies PAs, including PAs in both silicon and III-V technologies. A variety of challenges and performance limitations will be outlined. Then, we will present several recently published mm-Wave/sub-THz PA designs as examples to showcase the present capabilities. Future technology trends and potential devices/circuits solutions will be discussed as well.


Millimeter Wave and Sub-THz Power Amplifiers ― Enabling Technologies for Beyond-5G and 6G Wireless Networks

Future wireless standards require RF-sampling data converters to enable flexible multi-band operation over several GHz of instantaneous bandwidth. Efficient hardware organization in multi-antenna systems additionally requires co-integration of potentially many ADCs and DACs in a single chip with powerful data processing in the most advanced CMOS technologies. Besides the data converters, also a very high-quality clock generation, as well as calibration infrastructure must be integrated alongside the data converters. In this presentation we look at design examples of high-performance building blocks for such systems that have been implemented in one of the latest CMOS generations, with special emphasis on the digital assistance aspect in a DSP-heavy environment.

DSP-assisted RF-sampling data converters for 5G soft radio and beyond

The millimeter-wave (mmWave) and terahertz (THz) bands offer enormous bandwidth that is unparalleled, compared to the bandwidth available at lower microwave bands. This bandwidth has significant impact on the performance of wireless systems. The larger the channel bandwidth, the higher the throughput of wireless communication systems, and the higher the resolution of radar sensor systems. 
For the development of mmWave and THz wireless systems, advanced packaging platforms are required for system-integration of the ICs, antennas and other components required for system functionality. However, these platforms, also called antenna-in-package (AiP) platforms in published literature must meet some key requirements.
In this talk, the packaging requirements for mmWave and THz wireless applications are extensively discussed.


Packaging requirements for mmW & THz wireless applications

This talk will discuss the challenges to design and implement THz circuits in CMOS, as well as a discussion on applications. It will give an overview of the research results in this field by the MICAS group of KU Leuven, Belgium

THz circuits and applications

This presentation provides an overview of InP HBT integrated circuit technologies for mmWave and THz applications. Transistor and circuit performance will be reviewed with an emphasis on power amplifiers at mmWave and sub-THz frequencies. Heterogeneous integration techniques using wafer-scale 3D integration and device-scale microtransfer printing are also described.

InP technologies for mmW & THz wireless applications

The terahertz frequency range provides abundant bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless communication and enables data rates up to and above 100 Gbps. In this talk, I will present our early work on THz imaging and sensing with CMOS and SiGe HBTs. I will then present 6G wireless transceivers and discuss their performance and link impairments. I start with link budget considerations and address design trade-offs with respect to the used technology. The radio front-ends are manufactured in a SiGe BiCMOS 0.13um technology and operate at a tunable carrier of 220–260 GHz. The modules achieve data-rates from 20 to 100 Gbps with an EVM from 7% to 17% at a 1-meter distance using 16-QAM. I will further present our work on polarization diversity MIMO systems above 200 GHz. The MIMO link is established using a circular dual-polarization Tx and a dual-polarization Rx module. The polarization-diversity (left-handed circular polarization and right-handed circular polarization) is provided by a lens-coupled circularly polarized on-chip antenna. With this system, two independent data-streams of 55 Gb/s each were transmitted in parallel over a 1-meter line-of-sight distance, achieving an aggregated record data-rate of 110 Gbps.

How to Evaluate Efficient Deep Neural Network Approaches

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How to Evaluate Efficient Deep Neural Network Approaches

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Next from ESSCIRC ESSDERC Educational Events

Artificially-intelligent Closed-loop Neurostimulators for the Treatment of Neurological Disorders

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