United States

A switching of resistive memory cells leads to a local accumulation of Joules heat in the device. In resistive RAM (ReRAM) arrays of memory cells, the heat generated in one cell spreads via common electrode metal lines to the neighboring cells and may cause their performance degradation. In our study, we used a baseline Cu/TaOx/Pt cell with a variety of alternative inert electrode cells replacing the inert Pt electrode. The performance degradation results in a reduced number of switching cycles and, in extreme cases, even in a loss of a bit, caused by the rupture of the nanofilament. We propose a thermal analysis of the thermal cross-talk, describe its impact on cells&#39; electric performance, and identify three major mechanisms for the ReRAM reliability: (i) thermal conductivity, (ii) the specific heat capacity, and (iii) geometry of the electrodes. Several ReRAM arrays are manufactured to vary the thermal conductivity, specific heat, and geometry of the electrodes by depositing eight different inert electrodes: Pt(50 nm)/Ti(30 nm), Ru(50 nm)/Ti(30 nm), Co(50 nm)/Ti(30 nm), Pt(50 nm/Cu(100 nm)/Ti(30 nm), Pt(50 nm)/ Cu(200 nm)/Ti(30 nm), Ru(50 nm/Cr(30 nm), Ru(50 nm)/Ti(50 nm), and Rh(50 nm)/Cr(30 nm). The analysis handles the heat generation in nanostructures and its transfer to the nano-sized or micrometer-sized electrodes and how the heat transfer over the electrodes is transferred to nanofilaments of other memory cells sharing one common electrode. Using the proposed methodology, the experimentally found differences in the degradation of electric performance of the array cells performed under identical circumstances can be correctly predicted by the proposed thermal analysis using the material properties and geometry parameters of the electrodes. The analysis starts from the observation that the heat, Q, generated - typically between 3 μJ to 60 μJ - in a metallic nanofilament of a resistance Ron, - typically in the 1 kΩ to 100 kΩ range - if it were absorbed in the filament itself, it would lead according to the heat absorption equation of a body of mass m and specific heat capacity cs, Q=m×cs×ΔT, to a temperature higher than the temperature inside the sun of 2.7×107 oK. Temperature ΔT, this high is the result of the tiny volume of nanofilament of typically 5×10-18 cm-3. Since such a high temperature is impossible, the heat has to be accommodated in the ReRAM array otherwise, as it spreads to the more massive electrodes, depending on their mass (i.e. on their volume) and their specific heat capacity, and by the Newtonian losses which largely depend on the surface areas of the electrodes including the contact pads. Our analysis shows that the heat spreads across the electrodes w very quickly in the μs range due to the high thermal diffusivity, k, of the metallic electrodes. It can be shown that the typical time scale is given by τ=√(k×L), where L is e.g. the distance between two neighboring cells. Thus, within less than a second a steady state of temperature distribution is established resulting in linear dependence of the temperature distribution along the electrode when evaluating the heat conduction equation. The solution of the equation allows for determining the temperature of the passive neighboring cells when heated by an active memory cell. We have confirmed experimentally that the heat from the same heated filament spreads more efficiently and quickly along the Cu electrode than along the Pt electrode, caused by the thermal conductivity of Cu being 5.8 higher than that of Pt. In fact, we have confirmed experimentally that the reliability of the passive neighboring cells disposed along the Cy electrode is much worse than the reliability along the Pt electrode. The proposed thermal analysis allows predicting ReRAM critical switching voltages, the degradation of electrical performance, and the reliability of ReRAM devices contingent on the choice of the electrode materials and the total volume of the electrodes.

EMC 2023

Methodology for Mitigation of the Reliability of a Resistive RAM Memory Array Caused by Thermal Cross-Talk Between the Memory Cells

thermal cross-talk

resistive ram

memory

A switching of resistive memory cells leads to a local accumulation of Joules heat in the device. In resistive RAM (ReRAM) arrays of memory cells, the heat generated in one cell spreads via common electrode metal lines to the neighboring cells and may cause their performance degradation. In our study, we used a baseline Cu/TaOx/Pt cell with a variety of alternative inert electrode cells replacing the inert Pt electrode. The performance degradation results in a reduced number of switching cycles and, in extreme cases, even in a loss of a bit, caused by the rupture of the nanofilament. We propose a thermal analysis of the thermal cross-talk, describe its impact on cells' electric performance, and identify three major mechanisms for the ReRAM reliability: (i) thermal conductivity, (ii) the specific heat capacity, and (iii) geometry of the electrodes. Several ReRAM arrays are manufactured to vary the thermal conductivity, specific heat, and geometry of the electrodes by depositing eight different inert electrodes: Pt(50 nm)/Ti(30 nm), Ru(50 nm)/Ti(30 nm), Co(50 nm)/Ti(30 nm), Pt(50 nm/Cu(100 nm)/Ti(30 nm), Pt(50 nm)/ Cu(200 nm)/Ti(30 nm), Ru(50 nm/Cr(30 nm), Ru(50 nm)/Ti(50 nm), and Rh(50 nm)/Cr(30 nm). The analysis handles the heat generation in nanostructures and its transfer to the nano-sized or micrometer-sized electrodes and how the heat transfer over the electrodes is transferred to nanofilaments of other memory cells sharing one common electrode. Using the proposed methodology, the experimentally found differences in the degradation of electric performance of the array cells performed under identical circumstances can be correctly predicted by the proposed thermal analysis using the material properties and geometry parameters of the electrodes. The analysis starts from the observation that the heat, Q, generated - typically between 3 μJ to 60 μJ - in a metallic nanofilament of a resistance Ron, - typically in the 1 kΩ to 100 kΩ range - if it were absorbed in the filament itself, it would lead according to the heat absorption equation of a body of mass m and specific heat capacity cs, Q=m×cs×ΔT, to a temperature higher than the temperature inside the sun of 2.7×107 oK. Temperature ΔT, this high is the result of the tiny volume of nanofilament of typically 5×10-18 cm-3. Since such a high temperature is impossible, the heat has to be accommodated in the ReRAM array otherwise, as it spreads to the more massive electrodes, depending on their mass (i.e. on their volume) and their specific heat capacity, and by the Newtonian losses which largely depend on the surface areas of the electrodes including the contact pads. Our analysis shows that the heat spreads across the electrodes w very quickly in the μs range due to the high thermal diffusivity, k, of the metallic electrodes. It can be shown that the typical time scale is given by τ=√(k×L), where L is e.g. the distance between two neighboring cells. Thus, within less than a second a steady state of temperature distribution is established resulting in linear dependence of the temperature distribution along the electrode when evaluating the heat conduction equation. The solution of the equation allows for determining the temperature of the passive neighboring cells when heated by an active memory cell. We have confirmed experimentally that the heat from the same heated filament spreads more efficiently and quickly along the Cu electrode than along the Pt electrode, caused by the thermal conductivity of Cu being 5.8 higher than that of Pt. In fact, we have confirmed experimentally that the reliability of the passive neighboring cells disposed along the Cy electrode is much worse than the reliability along the Pt electrode. The proposed thermal analysis allows predicting ReRAM critical switching voltages, the degradation of electrical performance, and the reliability of ReRAM devices contingent on the choice of the electrode materials and the total volume of the electrodes.

technical paper

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

EMC is coordinated with the Device Research Conference (DRC). This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. 

AlN/GaN/AlN quantum-well (QW) HEMTs have emerged as a promising device technology for high-power applications such as next-generation communication networks and military defense systems [1-2]. Thanks to their strong carrier confinement, high thermal conductivity, and high breakdown electric field of the AlN back barrier, QW-HEMTs are promising for highly scaled high-speed transistors capable of power amplification at high temperatures. Moreover, HEMTs grown on single-crystal AlN substrates would provide higher reliability thanks to their low dislocation densities (~104 /cm2) and the absence of thermal boundary resistance with the substrate in contrast to AlN on SiC, sapphire or other substrates. However, in thin GaN QWs along a crystal polar direction, a strong internal electric field can arise due to large polarization effects. The important consequences of the vertical electric field and compressive strain in the electronic transport of the thin GaN channel is not yet fully understood. Therefore, in this report we present a combined experimental and theoretical study concerning homoepitaxial AlN/GaN/AlGaN QW-HEMTs, in which both the internal electric field as well as the strain in the GaN channel are systematically varied simultaneously. A series of AlN/GaN/AlGaN QW HEMTs with different QW thickness, ranging from 20 to 200 nm, are grown by molecular beam epitaxy on single-crystal AlN substrates [See Fig. 1(a)]. As the QW thickness increases, the vertical electric field in the GaN channel decreases, resulting in a re-distribution of the electronic wavefunction. These effects can be clearly seen from the self-consistent Schrödinger–Poisson simulations displayed in Fig. 1(b). Structural analysis was performed using atomic force microscopy (AFM) and high-resolution X-ray diffraction (HRXRD). The symmetric ω/2θ diffraction pattern, shown in Fig. 1(c), and the reciprocal space map (RSM) around the asymmetric (-105) reflection, displayed in Fig. 1(d), indicate the relaxation process of GaN layer as the channel thickness increases. The AFM scans, displayed in Fig. 2, reveal smooth surface morphologies with sub-nanometer root-mean-square roughness for all the samples. While clear atomic steps are observed on the HEMT with a 20-nm-thick GaN well, spiral hillocks start to appear on QW HEMTs with thicker GaN layers; this can stem from screw dislocations formed due to GaN relaxation. For both samples featuring a 50-nm-thick GaN well and a 200-nm-thick GaN well, the formation of visible cracks is observed. To examine the transport properties of the 2DEGs, hall-effect measurements were carried out at room temperature and 77 K. As shown in Fig. 3(a), the electron density increases and saturates with increasing GaN thickness, reaching 4.7x1013 /cm2. Meanwhile, a room-temperature sheet resistance of Rsh ~ 340 Ω/sqr was achieved in QW HEMTs with both thin and thick channels. To put these results in context, Fig. 3(b) compares the room temperature transport properties of all the reported 2DEGs in Al(Ga)N/GaN/Al(Ga)N heterostructures. A clear trend relating GaN thickness and mobility is observed. The high mobility HEMTs are achieved in thick and relaxed GaN layers with middle to low carrier densities. Since our samples are located within the high 2DEG density region, there exists room for further mobility improvement by lowering the carrier density in the channel. [1] Hickman et al. Semicond. Sci. Technol. 36 044001 (2021) [2] Yaita et al. IEEE Electron Device Lett., vol. 42, no. 11, pp. 1592–1595, Nov. 2021

High Electron Density AlN/GaN/AlGaN Quantum-Well HEMTs on Al-Polar Single-Crystal AlN Substrates

In this work, we demonstrate a pseudomorphic Al0.87Ga0.13N/Al0.64Ga0.36N metal-oxide-semiconductor HFETs (MOSHFET) on a single crystal bulk AlN substrate with linear ohmic contacts (RC ~ 4.3 Ωmm) enabled by a 30 nm thick reverse composition (x = 87% to 40%) graded contact making AlxGa1-xN layer using MOCVD. In addition to the thermal benefits, AlN substrates allow the growth of pseudomorphic epilayer structures for extreme bandgap (EBG) AlxGa1-xN channel HEMT devices (Al-composition > 60%, bandgap > 4.5 eV). The measured threading dislocation densities in our pseudomorphic epilayers were < 104 cm-2 which should lead to significantly lower gate-leakage thus promoting device stability.[1] These transistor devices showed Baliga Figure of Merit (BFOM) of 460 MW/cm2, which to date represents state-of-the-art performance for AlGaN-channel devices with similar composition. Device fabrication began with mesa isolation using Cl2-based ICP-RIE followed by Zr-stack metal deposition by e-beam evaporation as source/drain contacts, and rapid thermal annealing at 950 °C for 30 s under N2 environment. This was followed by an ICP-RIE etch of the graded layer from the access region, 10 nm SiO2 deposition as the gate oxide, Ni/Au gate, and Ti/Ni/Au probe pads deposition. Finally, the devices were embedded in 400 nm thick SiO2 film by PECVD to relieve the surface electric field for the breakdown voltage measurements. In addition to the bulk AlN substrates, identical devices were also fabricated where the same epilayer structure was deposited on AlN templates. These innovations enabled MOSHFET devices with on-state peak drain current density 610 mA/mm (at +2V gate bias), on-off ratio (107), a three-terminal off-state breakdown field > 3.7 MV/cm, and BFOM of 460 MW/cm2. Further optimization of surface passivation and edge termination could improve the effective off-state critical breakdown field (EC) to > 10 MV/cm, as measured in 2-terminal measurements by our team and others.[2,3] Deep scaling of EBG AlGaN power devices is enabled by this high EC. Compact devices have the additional advantage of reduced capacitance and other parasitics, allowing faster switching. However, the increased power density also leads to thermal limitations in overall system performance, e.g., current droop and premature failure, limiting deep-scaling of III-N power devices, due to poor heat removal through the currently used substrates with poor thermal conductivity (silicon, sapphire, Ga2O3).[4] We demonstrate using a novel thermal titration technique that the device on single crystal bulk AlN compared to identical structures on sapphire substrates shows 70% reduction in thermal impedance to 10 K-mm/W, a value that is comparable to SiC and copper heat-sinks. We will show that the improved electrical performance above is due to this enhanced thermal management from the bulk AlN substrate, arising from its intrinsic excellent thermal conductivity and high-temperature stability.[5] These advantages of EBG III-nitrides are attractive for post-GaN deep-scaled efficient and compact co-designed power electronics with passive thermal management, such as in consumer electronic chargers, and next-generation electric vehicles (EV).[6] [1] S. Rathkanthiwar, J. Houston Dycus, S. Mita, R. Kirste, J. Tweedie, R. Collazo, & Z. Sitar. Applied Physics Letters, 120(20), 202105 (2022). [2] K. Hussain, A. Mamun, R. Floyd, M. D. Alam, M. E. Liao, K. Huynh, ... & A. Khan. Applied Physics Express. (2023). [3] D. Khachariya, S. Mita, P. Reddy, S. Dangi, J. H. Dycus, P. Bagheri, ... & S. Pavlidis. Applied Physics Letters, 120(17), 172106 (2022). [4] R. L. Xu, M. M. Rojo, S. M. Islam, A. Sood, B. Vareskic, A. Katre, ... & E. Pop. Journal of Applied Physics, 126(18), 185105 (2019). [5] N. Yafune, S. Hashimoto, K. Akita, Y. Yamamoto, H. Tokuda, & M. Kuzuhara. Electronics letters, 50(3), 211-212 (2014). [6] T. Kachi. Japanese Journal of Applied Physics, 53(10), 100210 (2014).

Al0.64Ga0.36N Channel MOSHFET on Single Crystal Bulk AlN Substrate for Co-Designed Power Electronics

Wide bandgap GaN holds great promise for high-efficiency power conversion systems due to the excellent physical properties of GaN material. For GaN devices, vertical structure devices have attracted great attention after the lateral GaN-HEMT device since they have high current density, lower peak electric field at high voltage, and immunity to surface-related issues. GaN stability is a serious concern for predictable device behavior in real-world operations. For now, the reliability of vertical GaN devices still needs to be investigated systematically. In this work, the first comprehensive study of the reliability of GaN vertical P-I-N diode was presented. The device stability and parameter shift under high-temperature stress and current stress have been investigated. The failure mechanism of the device at high power density has been studied. For the high-temperature stress, first, the temperature of devices rising from 25 °C to 400 °C, and the forward curves of the device during temperature stress are shown in Fig.1. The extracted turn-on voltage and On-resistance are shown in Fig.2. At each temperature value, several curves were scanned in case of the transient instability at variable temperature. It shows that the turn-on voltage keeps decreasing with the temperature increase due to the energy band narrowing with increasing temperature. And the turn-on voltage can completely recover after the high-temperature stress is finished. For the On-resistance, it shows that the On-resistance decreases with the temperature increasing from 25°C to 100°C but is stable at each temperature. When the temperature is increased from 125°C to 400 °C, the On-resistance first increases and then decreases. However, the trend is not evident in this experiment. Therefore, another long-time temperature stress testing of 200°C and 400°C was done, as shown in Fig. 3 (forward curves). And the extracted On-resistance is shown in Fig. 4. For the temperature stress of 200°C, the On-resistance first decreases and then increases to larger than the original value. For the stress of 400°C, the On-resistance decreased and then was kept at a constant value. The reason that the device’s On-resistance changed during the temperature stress of 200°C is still under investigation. In addition, the On-resistance can recover from high temperatures. For the current stress testing (turn-on state), first, long-time current stress was finished. It showed that the GaN vertical P-I-N diode is very stable for long-time operation without any degradation. However, at the beginning of the stress, the device is not stable due to trapping behavior and carrier accumulation. As shown in Fig. 5, the current stress at voltages from 4V to 8V and a stress time of the 30s, 60s, 90s, and 120s were applied to a device, respectively. It shows that for the same voltage, the on-resistance (Fig. 6) will decrease to a certain value and then keep constant. This means the filling of the trapped states in the device is voltage-dependent. We also did reverse testing of the recovery of On-resistance at negative voltage stress. After the current stress process of Fig. 5, this device was applied to a negative voltage of -5 V, -10 V, -20 V, and -50 V, respectively. After each reverse voltage stress, the process in Fig. 5 was repeated, as shown in Fig. 7. It was shown that the On-resistance of the device shows voltage level dependent character again after -50 V stress, indicating that the trap and carrier accumulation can be recovered at a higher negative voltage. Fig. 8 shows the turn-on voltage of the device with different voltage and time stress. The shift of the turn-on voltage is smaller than 0.05 V, indicating that the GaN vertical P-I-N diode has good reliability of turn-on voltage. Fig. 9 shows the forward curve after high power density stress. The failure mechanism is still under investigation.

Reliability Study and Analysis of Vertical GaN Power Devices

Transparent conductive oxides (TCOs) are essential elements for photovoltaics and optoelectronic devices. In this work thin films of ZnO co-doped with In3+ and Ga3+ (IGZO) were deposited by atomic layer deposition onto various commercial and homegrown substrates to develop TCOs and characterized by X-ray diffraction, scanning electron microscopy, transmission electron microscopy, atomic force microscopy, optical spectroscopy, and Hall-effect measurements. The thin films exhibit structural stability, remarkable conductivity at room temperature, high visible range transparency, and a band gap near 3.42 eV. Optical and electrical characterization revealed a TCO figure of merit Φ = 8.66 × 10-2 Ω-3 for IGZO with a thickness of 164 nm surpassing Al-doped ZnO (AZO) TCOs and rivalling the industry standard ITO. Temperature-dependent electrical transport measurements of IGZO films revealed a fully degenerate semiconductor behavior.

Atomic Layer Deposition of Highly Conductive Highly Transparent Indium Gallium Doped Zinc Oxide Thin Films

Introduction: Titanium Dioxide (TiO2) is a semiconductor that can be found under Brookite, Rutile and Anatase phases, where the former has gained relevance due to its photocatalytic features, high chemical stability, low toxicity/cost, and strong oxidizing capacity under UV light [1]. Exposing TiO2 to UV light leads to the production of indirect electronical transition that enables the formation of reactive species, with free radical hydroxyl (HO) and superoxide (O2) that promotes decomposition of organic contaminants [2]. Two techniques will be compared. Atomic Layer Deposition (ALD) is physical and requires two vapor precursors injections inside a chamber separated by the purge of an inert gas, and each precursor saturates the surface of the substrate leading to the formation of the TiO2 thin film. Hence, the ALD methodology is considered a stepped self-limiting technic [3], where the thickness of the thin film relies on the number of deposited cycles under half vacuum pressure conditions (0.1 torr). Sol-Gel is a chemical technique applied at room temperature and atmospheric pressure conditions, where simultaneous reactions are produced: hydrolysis and condensation [4]. Initially, the hydrolysis requires a metallic precursor (titanium alkoxide), solvents and acidification of the solution, which results in the formation of Titanium Hydroxides and the condensation process finally leads to the Titanium Dioxide synthesis [5]. In this work, TiO2 thin films are generated over glass substrates previously cleaned through DI water, 2propanol and acetone. For ALD the Titanium Alkoxide Tetraisopropyl Orthotitanate (Ti[OCH(CH3)2]4) was taken as precursor, and vaporized water for the formation of TiO2; under a Ni atmosphere at 20 sccm, with 1100 cycles (20 nm thick), a working temperature fixed at 200 C and pressure of 2.45x10-1 torr. For Sol-Gel, the solution was also prepared using Ti[OCH(CH3)2]4, but with ethanol (CH3CH2OH), acetic acid (CH3COOH), H2O2 and DI water, as explored in [5-7]. Solution is spin coated over hydrolyzing substrate (H2SO4 + H2O2 in 3:1 concentration. Manufactured films from both techniques, were taken to an annealing process at 450 C and 550 C, under a Ni atmosphere with a gas flux of 4000 sccm during 1 hour. The characterization of TiO2 thin films was realized before and after the annealing process, starting from X-Ray Diffraction (XRD) to the crystallin phase of the TiO2 anatase on each treatment, in order to measure the intensity of the phase in the plane (101) with an angle of 25.16±0.2° (Fig. 1) [2]. Also, the absorption spectrum was measured using the Lambert-Beer Law [8] and the bandgap energy by direct gap of the semiconductor was estimated as a function of temperature (Fig. 2); moreover, the morphology of the films surface was observed with the Scanning Eletron Microscopy (SEM) technique and the elemental analysis of the films by energy dispersive X-ray spectroscopy (EDX). Finally, the resistivity was measured using the Van der Pauw 4-point technique and the charge mobility was analyzed with Hall effect (Fig. 2). References [1] A. Ibrahim, W. Phoohinkong, W. Mekprasart, and W. Pecharapa, Mater. Today Proc., vol. 5, no. 5, pp. 10903–10909, 2018. [2] R. Katal, S. Masudy-Panah, M. Tanhaei, M. H. D. A. Farahani, and H. Jiangyong, Chem. Eng. J., vol. 384, no. October 2019, p. 123384, 2020. [3] V. Pore, A. Rahtu, M. Leskelä, M. Ritala, T. Sajavaara, and J. Keinonen, Chem. Vap. Depos., vol. 10, no. 3, pp. 143–148, 2004 [4] Brinker C. Jeffrey, p. 462, 1990. [5] M. B. Tahir, K. Nadeem, M. Hafeez, and S. Firdous, Indian J. Pure Appl. Phys., vol. 55, no. 10, pp. 716–721, 2017. [6] M. Urbonavicius, S. Varnagiris, S. Sakalauskaite, E. Demikyte, S. Tuckute, and M. Lelis, Catalysts, vol. 11, no. 7, 2021. [7] C. Villanueva Jaramillo, A. M. Pedroza, J. C. Salcedo, A. K. Carrascal Camacho, and A. E. Florido Cuellar, pp. 1–125, 2011. [8] G. L. Tian, H. B. He, and J. Da Shao, Chinese Phys. Lett., vol. 22, no. 7, pp. 1787–1789, 2005.

Atomic Layer Deposition (ALD) and Sol-Gel Techniques Comparison from the Perspective of TiO2 Thin-Films Fabrication

Self-aligned channel regions in thin-film transistors (TFTs) have advantages in reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. A common method used to fabricate self-aligned a-Si:H TFTs is to utilize a through-glass exposure of photoresist which is blocked by the opaque metal bottom-gate electrode [1,2]. This process does not require an additional photomask or lithographic alignment, and thus supports low production cost. Sputtered IGZO has been introduced into flat panel display product manufacturing, exhibiting a channel mobility of approximately an order of magnitude higher than a-Si:H. The working source/drain electrodes in IGZO TFTs can be direct metal contact regions to the IGZO, without the need for additional processes such as doping to render the IGZO conductive. Proper metallurgy and annealing processes can provide ohmic behavior with minimal series resistance, however this usually requires several microns of gate-to-source/drain overlap to ensure such behavior. This work provides an interpretation of donor activation in self-aligned bottom-gate IGZO TFTs with ion-implantation of boron (11B+) and phosphorus (31P+) species as the source/drain treatment. In previous investigations of boron implantation, utilizing an anneal-implant sequence resulted in self-aligned devices with transfer characteristics comparable to non-self-aligned TFTs. A left shift in transfer characteristics was observed following thermal stress at 175 °C which is not consistent with recent work from alternate sources which have shown boron implanted devices temperature stable at 200 °C [3,4]. It is hypothesized that this is the result of implant species contamination due to the presence of hydrogen in the implant gas distribution system. In contrast, following an implant-anneal sequence at 400 °C did not support an electrically active species. The implant-anneal strategy seems to result in a different bonding arrangement which does not support donor-like behavior related to boron. Self-aligned phosphorus implants present promising behavior using the implant-anneal strategy, potentially serving as a lightly doped drain (LDD) structure for sub-micron scaled devices.

Donor Activation in Boron and Phosphorus Implanted Self-Aligned Bottom-Gate IGZO TFTs

We report the successful fabrication and characterization of thin film transistors (TFTs) with a significant ~95.7% reduction on the saturation currents thanks to ultraviolet ozone (UVO) and controlled annealing treatments. Such TFTs (Figure 1) were designed for autonomous microrobotic applications. On this specific study we exposed the TFTs to a 3 min ultraviolet ozone (UVO) with 184.5 nm (17%) and 253.7 nm (83%) UV light emissions at a constant light intensity (28-32 mW cm−2), together with 1 hour annealing treatment at 300 °C to yield contact resistance of 74.5±1.16 Ω and sheet resistance of 5.376 Ω/square. Although, defects and uniformity of materials usually affect the performance of TFTs such as threshold voltage, contact resistance, and output current [4,5], the consistent reduction of saturation currents (~252 μA @ Vg=50 V) obtained after UVO treatment (Figure 2) are evidence that oxygen vacancies were reduced, and metal-oxygen bonding were increased. TFT are versatile semiconductor devices with wide applications, ranging from liquid crystal displays to flexible and transparent electronic devices [1-3] expected to have low drain-source currents during saturation to reduce de energy consumption, especially critical in autonomous small scale robotic applications. The proposed TFTs were fabricated over insulated (100 nm SiO2) P-type (100) silicon substrate with bottom-gate/top-contact architecture. The device cross section shown in Figure 1a, contains 50 nm semiconductor layer of amorphous Indium-gallium-zinc oxide (InGaZnO4) via sputtering; 10 nm/50 nm Cr/Au electrode layers deposited by electron beam evaporation for drain, source and gate; and 10 nm of Al2O3 grown via atomic layer deposition as dielectric. We also designed and array of TFTs with different sizes (channel with and length) and test features, to extract important parameters for compact modeling. Lengths ranges between 8 µm to 160 μm and widths between 10 µm to 1000 μm. Test features include transfer length method (TLM), capacitance extraction, and four-point van der Pauw for hall probe measurements to extract mobility. The fully fabricated chip and TFT are shown in Figure 1b-1c. I-V curves were measured for all channel dimensions and saturation currents are summarized in Figure 3. As expected, the saturation current decreases with the length and increases with TFTs width, useful relationships that provide reference for designing specific power on future TFTs generations with improved performance after UVO and annealing technique. Acknowledgement: The authors would like to thank the support from the Mechanical and Aerospace Engineering Department. University of California, Irvine. References: [1] Hays, D. C., Gila, B. P., Pearton, S. J., & Ren, F. (2017). Energy band offsets of dielectrics on InGaZnO4. Applied Physics Reviews, 4(2), 021301. [2] Zhou, X., Cao, H., Zhou, Z., Cao, J., & Yu, J. (2017). Structural, electrical and optical properties of InGaZnO4InGaZnO4 and In29Sn3O48In29Sn3O48: a first-principles study. Journal of Computational Electronics, 16(2), 280-286. [3] Nomura, K., Takagi, A., Kamiya, T., Ohta, H., Hirano, M., & Hosono, H. (2006). Amorphous oxide semiconductors for high-performance flexible thin-film transistors. Japanese journal of applied physics, 45(5S), 4303. [4] McDonnell, S., Addou, R., Buie, C., Wallace, R. M., & Hinkle, C. L. (2014). Defect-dominated doping and contact resistance in MoS2. ACS nano, 8(3), 2880-2888. [5] Suemori, K., Uemura, S., Yoshida, M., Hoshino, S., Takada, N., Kodzasa, T., & Kamata, T. (2008). Influence of fine roughness of insulator surface on threshold voltage stability of organic field-effect transistors. Applied Physics Letters, 93(3), 264.

Improved Electrical Performance of InGaZnO4 Thin-Film Transistors with UV Ozone Treatment

Two-dimensional (2D) van der Waals transparent conducting metal oxides (TCOs) have recently emerged as a promising platform for fabricating flexible optoelectronic devices, offering high mobility, high transparency, and improved mechanical flexibility. This class of 2D oxides can be synthesized at low temperatures (< 180 °C) without vacuum by utilizing the unique physics of liquid metal surface oxides. Here we report continuous liquid metal printing for scalable fabrication of high-performance 2D TCOs compatible with polymer substrates. We apply a spontaneous Cabrera Mott growth at low-temperatures afforded by the low melting point of In, Ga, Sn, and their alloys. In our continuous liquid metal printing (CLMP) method, these metal droplets serve as the source material for simultaneously growing and depositing these films via adhesion of the 2-3 nm thick solid oxide skin over large areas (~ 100 cm2). The high speed of this roller-based deposition method (> 6 meters/minute) is also particularly promising because Cabrera Mott synthesis naturally yields high conductivity, sub-stoichiometric oxides via their oxidation from the metallic phase. This allows the use of a rapid process, eliminating thermal post-annealing steps otherwise necessary for low-temperature metal oxides, opening up greater opportunities for utilizing lower cost plastic substrates. In this presentation, we demonstrate a new class of layered TCO heterostructures exploiting modulation doping interactions between 2D InOx and 2D GaOx. We characterize the crystallinity of these 2D oxide films as a function of deposition temperature within the range of plastic substrates (160 °C to 240 °C) by XRD and apply TEM to observe the large plate-like cubic InOx grain structure. These overlapped grain morphologies lead to high conductivity (up to 600 S/cm) despite the exceptionally low total processing time (3s per layer) and low temperatures (180 °C). Through XPS, UV-Vis, and Hall characterization, we examine the modulation doping effect induced by the InOx / GaOx interface in these multilayer TCOs. UV-Vis absorption spectroscopy reveals the impact that modulation doping can enhance visible range transparency through a Burstein Moss effect-induced optical bandgap widening. We characterize the flexibility of these 2D TCOs in comparison with sputtered ITO electrodes on plastic substrates, showing how the ultrathin nature provides substantially greater strain tolerance under cyclic bending. These results show how interfacial modulation doping interactions can be used to control and enhance the electronic properties of 2D oxides beyond the state of the art for low-temperature processed metal oxides.

Continuous Liquid Metal Printing of High-Performance 2D Oxide Heterostructures

In this study, we demonstrate the utility of impurity band conduction in overcoming the limitations of conventional p-type doping in Al-rich aluminum gallium nitride (AlGaN). First, a model is developed to understand the impurity band conduction mechanism in Mg-doped AlGaN. It is hypothesized that at high Mg doping concentrations (mid-1019 cm-3) -below the Mott transition-, the overlap of the Mg dopant states can cause the dopant energy level to split into a quasi-continuous impurity band. This provides an alternate route for conduction, where the carriers can propagate through the impurity band with a much-reduced activation energy as compared to the relatively large Mg ionization energy required for the valence band transport. It is worthwhile to note that the presence of compensating point defects can disrupt the overlap of the Mg orbitals and, hence, impede the formation of the impurity band. Mg-doped Al-rich AlGaN epilayers were grown on sapphire and single-crystal AlN substrates by metalorganic chemical vapor deposition. In accordance with the model, relatively heavy Mg doping in conjunction with compensation control was found to be critical to induce the impurity band formation. Record-low p-type resistivities of 9.7 and 37 Ωcm were achieved in Al0.7Ga0.3N and Al0.8Ga0.2N films grown on the native substrate. The resistivity exhibited shallow activation energy of ~30 meV for a wide temperature range of 150-500K. Valence band conduction associated with a large Mg ionization energy was observed to dominate above 500K. Interestingly, the Hall coefficient data was found to deviate from classical semiconductor physics. The apparently anomalous results were attributed to the fact that the Hall effect associated with the carriers propagating in the impurity band differs qualitatively from the quasi-free motion of holes in the valence band leading to a fundamentally different Hall scattering factor. This work demonstrates the utility of impurity band conduction to achieve technologically relevant p-type conductivity in Al-rich AlGaN. Al-rich AlGaN devices are poised to enable a host of optoelectronic applications owing to their desired properties such as low size, weight, and potential operating power. While Si doping has been demonstrated to be effective in achieving n-type Al-rich AlGaN films, efficient p-type doping remains a significant challenge. Mg, the most explored p-type dopant in AlGaN presents a rather high ionization energy of >400 meV. This creates a fundamental bottleneck as only a small fraction of the Mg atoms ionizes at room temperature to generate free holes. This results in a high resistivity >100 Ωcm in Mg-doped Al-rich AlGaN grown via the conventional Mg doping approach. While alternate doping approaches such as short-period superlattices, composition modulation, and Mg delta doping allow for low lateral resistivity in p-AlGaN the vertical conduction is limited due to the barriers associated with the periodic oscillation of the energy bands. The polarization-graded AlGaN approach, on the other hand, necessitates the grading toward Ga-rich compositions to achieve high hole concentration and to favor the Ohmic contact formation. This approach suffers from UV-C absorption loss in the p-type layer, significantly decreasing the light extraction efficiency in optoelectronic devices. Therefore, it is of significance to devise techniques for achieving low p-type resistivity in Al-rich AlGaN without modulating the composition or the doping profile.

Achieving Technologically Relevant P-Type Conductivity in Al-Rich (>70% Al) AlGaN Using Impurity Band Conduction

Spin-orbit torque magnetic random-access memory (SOT-MRAM) has received extensive interest in the memory industry. Recent efforts have focused on a heavy metal (HM)/ferromagnet (FM) bilayer with an additional HM capping strip to deterministically switch the magnetization [1]. This paper investigates the switching behaviors of SOT-MRAM utilizing this structure with micromagnetic simulations coupled to the drift-diffusion spin transport model [2]. The three-dimensional spin transport solver self-consistently calculates the charge currents, spin currents, and spin accumulations for arbitrary geometries and multi-layer structures without importing a computed current density [2]. This work uses a simple W/CoFeB/MgO structure to realize deterministic magnetization switching based on the HM capping strip method, which can be readily adopted in magnetic tunnel junctions. Figure 1(c) shows the simulated structure. In the simulations, the FL magnetization starts from an initial state of Mz/Ms = +1. The pulse current density J is injected into the HM along the negative x-direction with a duration of 2 ns. After the pulse, the magnetization switches to the negative z-axis through the relaxation process. In a conventional HM/FM, there is no additional HM capping strip. The My/Ms approaches 0 and My/Ms approaches +1 after the current pulse, which leads to a non-deterministic state when the current is removed. However, Mz/Ms crosses over 0 and reaches a negative remnant value. After removing the current, Mz/Ms proceeds toward a downstate Mz/Ms=-1 and causes deterministic magnetization. We investigate the mechanism behind the HM-capping-strip-induced deterministic magnetization switching [2]. The spin accumulation distribution on the bottom HM interface is the key to understanding deterministic switching. With an HM strip capping on the HM layer, some non-negligible negative Sz is observed near the center y position, which is immediately above the FL. This negative Sz induces an additional negative z-direction spin torque when Mx/Ms=0, My/Ms=+1, and Mz/Ms=0 is reached. Therefore, a negative is observed under sufficiently large J. This is the critical factor of deterministic magnetization switching for the proposed structure. To understand the origin of this non-negligible Sz on the bottom HM interface, Figs. 3 show the origination from the negative z-direction spin on the edge of the HM capping strip. By characterizing the system with an accurate spin-flip length of tungsten, the drift-diffusion spin transport solver with a negative z spin on the edge of the HM capping strip leads to a non-negligible negative Sz on the bottom HM interface. Further, the spin accumulation along the y-axis on the bottom HM interface has an opposing polarity when applying the opposite direction of J. Thus, the magnetization switches from Mz/Ms = -1 to Mz/Ms = 1 by changing the polarity of the current. Mz/Ms reaches different under various J. This depends strongly on the current direction and magnitude, which indicates that deterministic bipolar switching can be achieved by changing the polarity of the current. A larger mr results in improved switching behaviors because it prevents the magnetization from stochastically switching under the interference of thermal fluctuations. Furthermore, Fig. 4(a) indicates that a larger mr induces a faster relaxation process when the current is removed, which gives a faster operating speed for the MRAM cell. Therefore, a larger current does not guarantee a higher switching speed. Instead, J with a magnitude slightly larger than Jc gives the ideal results. The relationship between Jc and w is also established, where Fig. 6(a) shows the SOT switching loops with different w. As w increases, Jc decreases. Instead of choosing the HM strip edge at the middle of the FL, the Jc minimum occurs near w=35 nm. [1] 35Y. Li, N. Zhang, and K. Wang, Sci. China Inf. Sci. 65, 122404 (2022) [2] S. Lepadatu, J. Appl. Phys. 128, 243902 (2020).

Methodology for Mitigation of the Reliability of a Resistive RAM Memory Array Caused by Thermal Cross-Talk Between the Memory Cells

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Methodology for Mitigation of the Reliability of a Resistive RAM Memory Array Caused by Thermal Cross-Talk Between the Memory Cells

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