United States

Convolutional neural networks (CNNs) are a powerful tool in computer vision, commonly used for image segmentation and classification. The accuracy and scope of CNNs can generally be improved be increasing the complexity of the network, such as the number of layers, channels, or fully connected layers. However, increasing CNN complexity comes at the cost of increased power consumption and calculation time. The first layer of a CNN detects low level features, such as edges. If an optical system was designed to perform low level feature detection, that task could be offloaded from the computer, allowing for faster, lower-power consumption CNNs, without sacrificing accuracy. Optical edge detection has been explored previously, though current methods have limitations that prevent their use in many practical applications, such as requiring polarized or coherent illumination, requiring bulky 4f systems, or being limited to small apertures. We have designed and experimentally demonstrated systems which overcome these limitations, allowing for broadband optical edge detection of incoherent thermal emission with optimized signal to noise ratio. Further, UNet image segmentation networks trained using our simulated models as an optical front end demonstrated an improved Dice coefficient (from 0.877 to 0.899) with 4 times fewer FLOPs compared to a similar UNet architecture trained on raw images. Our optical edge detection system combines the design flexibility of metasurfaces with the broadband focusing capability of refractive optics. Using gradient descent based inverse design, the metasurface is designed to modify the point spread function (PSF) of the combined optic system to emulate an edge detection kernel. Edge detection kernels have both positive and negative values, which cannot normally be achieved in an incoherent PSF; this can be circumvented by splitting the PSF into positive and negative components, which produce two images that are digitally subtracted produce a single edge image. This is achieved with a single polarization sensitive metasurface which, in conjunction with a refractive lens, forms independent images corresponding to the positive and negative PSF components using two orthogonal polarization states, which can be simultaneously captured using a polarimetry enabled LWIR camera.

EMC 2023

Large-Scale Inversely Designed Metasurfaces for Broadband LWIR Optical Edge Detection

edge detection

inverse design

metasurfaces

After two years of virtual conferences, we're excited to host EMC 2022 in person at The Ohio State University in Columbus, Ohio. In addition to cutting-edge technical presentations given in multiple parallel sessions, opportunities to network with colleagues will be present throughout the conference. The size and format of the meeting makes networking easy, whether you have been coming to the conference for many years or are a first-time attendee.

EMC is coordinated with the Device Research Conference (DRC), which will be held the same week, from June 26-29. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

For information on the 80th Device Research Conference, please visit the DRC 2022 website.



EMC 2022

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

technical paper

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

EMC is coordinated with the Device Research Conference (DRC). This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. 

AlN/GaN/AlN quantum-well (QW) HEMTs have emerged as a promising device technology for high-power applications such as next-generation communication networks and military defense systems [1-2]. Thanks to their strong carrier confinement, high thermal conductivity, and high breakdown electric field of the AlN back barrier, QW-HEMTs are promising for highly scaled high-speed transistors capable of power amplification at high temperatures. Moreover, HEMTs grown on single-crystal AlN substrates would provide higher reliability thanks to their low dislocation densities (~104 /cm2) and the absence of thermal boundary resistance with the substrate in contrast to AlN on SiC, sapphire or other substrates. However, in thin GaN QWs along a crystal polar direction, a strong internal electric field can arise due to large polarization effects. The important consequences of the vertical electric field and compressive strain in the electronic transport of the thin GaN channel is not yet fully understood. Therefore, in this report we present a combined experimental and theoretical study concerning homoepitaxial AlN/GaN/AlGaN QW-HEMTs, in which both the internal electric field as well as the strain in the GaN channel are systematically varied simultaneously. A series of AlN/GaN/AlGaN QW HEMTs with different QW thickness, ranging from 20 to 200 nm, are grown by molecular beam epitaxy on single-crystal AlN substrates [See Fig. 1(a)]. As the QW thickness increases, the vertical electric field in the GaN channel decreases, resulting in a re-distribution of the electronic wavefunction. These effects can be clearly seen from the self-consistent Schrödinger–Poisson simulations displayed in Fig. 1(b). Structural analysis was performed using atomic force microscopy (AFM) and high-resolution X-ray diffraction (HRXRD). The symmetric ω/2θ diffraction pattern, shown in Fig. 1(c), and the reciprocal space map (RSM) around the asymmetric (-105) reflection, displayed in Fig. 1(d), indicate the relaxation process of GaN layer as the channel thickness increases. The AFM scans, displayed in Fig. 2, reveal smooth surface morphologies with sub-nanometer root-mean-square roughness for all the samples. While clear atomic steps are observed on the HEMT with a 20-nm-thick GaN well, spiral hillocks start to appear on QW HEMTs with thicker GaN layers; this can stem from screw dislocations formed due to GaN relaxation. For both samples featuring a 50-nm-thick GaN well and a 200-nm-thick GaN well, the formation of visible cracks is observed. To examine the transport properties of the 2DEGs, hall-effect measurements were carried out at room temperature and 77 K. As shown in Fig. 3(a), the electron density increases and saturates with increasing GaN thickness, reaching 4.7x1013 /cm2. Meanwhile, a room-temperature sheet resistance of Rsh ~ 340 Ω/sqr was achieved in QW HEMTs with both thin and thick channels. To put these results in context, Fig. 3(b) compares the room temperature transport properties of all the reported 2DEGs in Al(Ga)N/GaN/Al(Ga)N heterostructures. A clear trend relating GaN thickness and mobility is observed. The high mobility HEMTs are achieved in thick and relaxed GaN layers with middle to low carrier densities. Since our samples are located within the high 2DEG density region, there exists room for further mobility improvement by lowering the carrier density in the channel. [1] Hickman et al. Semicond. Sci. Technol. 36 044001 (2021) [2] Yaita et al. IEEE Electron Device Lett., vol. 42, no. 11, pp. 1592–1595, Nov. 2021

High Electron Density AlN/GaN/AlGaN Quantum-Well HEMTs on Al-Polar Single-Crystal AlN Substrates

In this work, we demonstrate a pseudomorphic Al0.87Ga0.13N/Al0.64Ga0.36N metal-oxide-semiconductor HFETs (MOSHFET) on a single crystal bulk AlN substrate with linear ohmic contacts (RC ~ 4.3 Ωmm) enabled by a 30 nm thick reverse composition (x = 87% to 40%) graded contact making AlxGa1-xN layer using MOCVD. In addition to the thermal benefits, AlN substrates allow the growth of pseudomorphic epilayer structures for extreme bandgap (EBG) AlxGa1-xN channel HEMT devices (Al-composition > 60%, bandgap > 4.5 eV). The measured threading dislocation densities in our pseudomorphic epilayers were < 104 cm-2 which should lead to significantly lower gate-leakage thus promoting device stability.[1] These transistor devices showed Baliga Figure of Merit (BFOM) of 460 MW/cm2, which to date represents state-of-the-art performance for AlGaN-channel devices with similar composition. Device fabrication began with mesa isolation using Cl2-based ICP-RIE followed by Zr-stack metal deposition by e-beam evaporation as source/drain contacts, and rapid thermal annealing at 950 °C for 30 s under N2 environment. This was followed by an ICP-RIE etch of the graded layer from the access region, 10 nm SiO2 deposition as the gate oxide, Ni/Au gate, and Ti/Ni/Au probe pads deposition. Finally, the devices were embedded in 400 nm thick SiO2 film by PECVD to relieve the surface electric field for the breakdown voltage measurements. In addition to the bulk AlN substrates, identical devices were also fabricated where the same epilayer structure was deposited on AlN templates. These innovations enabled MOSHFET devices with on-state peak drain current density 610 mA/mm (at +2V gate bias), on-off ratio (107), a three-terminal off-state breakdown field > 3.7 MV/cm, and BFOM of 460 MW/cm2. Further optimization of surface passivation and edge termination could improve the effective off-state critical breakdown field (EC) to > 10 MV/cm, as measured in 2-terminal measurements by our team and others.[2,3] Deep scaling of EBG AlGaN power devices is enabled by this high EC. Compact devices have the additional advantage of reduced capacitance and other parasitics, allowing faster switching. However, the increased power density also leads to thermal limitations in overall system performance, e.g., current droop and premature failure, limiting deep-scaling of III-N power devices, due to poor heat removal through the currently used substrates with poor thermal conductivity (silicon, sapphire, Ga2O3).[4] We demonstrate using a novel thermal titration technique that the device on single crystal bulk AlN compared to identical structures on sapphire substrates shows 70% reduction in thermal impedance to 10 K-mm/W, a value that is comparable to SiC and copper heat-sinks. We will show that the improved electrical performance above is due to this enhanced thermal management from the bulk AlN substrate, arising from its intrinsic excellent thermal conductivity and high-temperature stability.[5] These advantages of EBG III-nitrides are attractive for post-GaN deep-scaled efficient and compact co-designed power electronics with passive thermal management, such as in consumer electronic chargers, and next-generation electric vehicles (EV).[6] [1] S. Rathkanthiwar, J. Houston Dycus, S. Mita, R. Kirste, J. Tweedie, R. Collazo, & Z. Sitar. Applied Physics Letters, 120(20), 202105 (2022). [2] K. Hussain, A. Mamun, R. Floyd, M. D. Alam, M. E. Liao, K. Huynh, ... & A. Khan. Applied Physics Express. (2023). [3] D. Khachariya, S. Mita, P. Reddy, S. Dangi, J. H. Dycus, P. Bagheri, ... & S. Pavlidis. Applied Physics Letters, 120(17), 172106 (2022). [4] R. L. Xu, M. M. Rojo, S. M. Islam, A. Sood, B. Vareskic, A. Katre, ... & E. Pop. Journal of Applied Physics, 126(18), 185105 (2019). [5] N. Yafune, S. Hashimoto, K. Akita, Y. Yamamoto, H. Tokuda, & M. Kuzuhara. Electronics letters, 50(3), 211-212 (2014). [6] T. Kachi. Japanese Journal of Applied Physics, 53(10), 100210 (2014).

Al0.64Ga0.36N Channel MOSHFET on Single Crystal Bulk AlN Substrate for Co-Designed Power Electronics

Wide bandgap GaN holds great promise for high-efficiency power conversion systems due to the excellent physical properties of GaN material. For GaN devices, vertical structure devices have attracted great attention after the lateral GaN-HEMT device since they have high current density, lower peak electric field at high voltage, and immunity to surface-related issues. GaN stability is a serious concern for predictable device behavior in real-world operations. For now, the reliability of vertical GaN devices still needs to be investigated systematically. In this work, the first comprehensive study of the reliability of GaN vertical P-I-N diode was presented. The device stability and parameter shift under high-temperature stress and current stress have been investigated. The failure mechanism of the device at high power density has been studied. For the high-temperature stress, first, the temperature of devices rising from 25 °C to 400 °C, and the forward curves of the device during temperature stress are shown in Fig.1. The extracted turn-on voltage and On-resistance are shown in Fig.2. At each temperature value, several curves were scanned in case of the transient instability at variable temperature. It shows that the turn-on voltage keeps decreasing with the temperature increase due to the energy band narrowing with increasing temperature. And the turn-on voltage can completely recover after the high-temperature stress is finished. For the On-resistance, it shows that the On-resistance decreases with the temperature increasing from 25°C to 100°C but is stable at each temperature. When the temperature is increased from 125°C to 400 °C, the On-resistance first increases and then decreases. However, the trend is not evident in this experiment. Therefore, another long-time temperature stress testing of 200°C and 400°C was done, as shown in Fig. 3 (forward curves). And the extracted On-resistance is shown in Fig. 4. For the temperature stress of 200°C, the On-resistance first decreases and then increases to larger than the original value. For the stress of 400°C, the On-resistance decreased and then was kept at a constant value. The reason that the device’s On-resistance changed during the temperature stress of 200°C is still under investigation. In addition, the On-resistance can recover from high temperatures. For the current stress testing (turn-on state), first, long-time current stress was finished. It showed that the GaN vertical P-I-N diode is very stable for long-time operation without any degradation. However, at the beginning of the stress, the device is not stable due to trapping behavior and carrier accumulation. As shown in Fig. 5, the current stress at voltages from 4V to 8V and a stress time of the 30s, 60s, 90s, and 120s were applied to a device, respectively. It shows that for the same voltage, the on-resistance (Fig. 6) will decrease to a certain value and then keep constant. This means the filling of the trapped states in the device is voltage-dependent. We also did reverse testing of the recovery of On-resistance at negative voltage stress. After the current stress process of Fig. 5, this device was applied to a negative voltage of -5 V, -10 V, -20 V, and -50 V, respectively. After each reverse voltage stress, the process in Fig. 5 was repeated, as shown in Fig. 7. It was shown that the On-resistance of the device shows voltage level dependent character again after -50 V stress, indicating that the trap and carrier accumulation can be recovered at a higher negative voltage. Fig. 8 shows the turn-on voltage of the device with different voltage and time stress. The shift of the turn-on voltage is smaller than 0.05 V, indicating that the GaN vertical P-I-N diode has good reliability of turn-on voltage. Fig. 9 shows the forward curve after high power density stress. The failure mechanism is still under investigation.

Reliability Study and Analysis of Vertical GaN Power Devices

Transparent conductive oxides (TCOs) are essential elements for photovoltaics and optoelectronic devices. In this work thin films of ZnO co-doped with In3+ and Ga3+ (IGZO) were deposited by atomic layer deposition onto various commercial and homegrown substrates to develop TCOs and characterized by X-ray diffraction, scanning electron microscopy, transmission electron microscopy, atomic force microscopy, optical spectroscopy, and Hall-effect measurements. The thin films exhibit structural stability, remarkable conductivity at room temperature, high visible range transparency, and a band gap near 3.42 eV. Optical and electrical characterization revealed a TCO figure of merit Φ = 8.66 × 10-2 Ω-3 for IGZO with a thickness of 164 nm surpassing Al-doped ZnO (AZO) TCOs and rivalling the industry standard ITO. Temperature-dependent electrical transport measurements of IGZO films revealed a fully degenerate semiconductor behavior.

Atomic Layer Deposition of Highly Conductive Highly Transparent Indium Gallium Doped Zinc Oxide Thin Films

The mid-infrared wavelength range (MIR: 3-30 µm) is of significant technological importance. Many of its applications are well-served by leveraging techniques capable of enhancing light-matter interaction. Phononic systems, which leverage excitations of the crystal lattice coupled to electromagnetic modes, offer one potential approach. The negative real permittivity of a phononic material, in the material’s Reststrahlen Band, results in an optical response similar to that of plasmonic materials, though with lower loss (small imaginary permittivity). In the MIR, strongly polar AlN, with a high-energy longitudinal optical (LO) phonon at a free-space wavelength of 11.2 µm, is an intriguing phononic system, with negative permittivity extending from LO phonon wavelength to the transverse optical (TO) phonon wavelength of 15.9 µm[1]. In this work, we investigate periodic arrays of AlN-capped nanowires supporting a variety of unique phononic modes. We demonstrate localized surface phonon resonances (LSPhR) in the AlN nanostructures, in the frequency range bounded by AlN’s LO and TO phonon energies. We also demonstrate that the nano-pillar growth regime allows for normal incidence coupling to the Berreman mode which is observed in thin films at epsilon-near-zero (ENZ) permittivity (at LO phonon energy) for light incident at large grazing angles. The nanowires are grown by plasma-assisted MBE[2] on a patterned silicon wafer, which serves as the template for GaN nanowire growth, upon which AlN caps are grown. On a silicon wafer, after a series of buffer layer growths, a 70 nm Si3N4 growth mask is deposited on the top GaN buffer layer, and the growth mask is then patterned (by e-beam lithography) and etched to provide apertures to the underlying GaN with 1 µm period and varying diameters. GaN nanowires 1.8 μm in height are grown in the apertures, followed by an AlN cap of 210 nm, above the GaN nanowires. Periodic arrays of AlN-capped GaN nanowires were grown with varying aperture dimensions, resulting in nanowires with diameters of ∼ 210, 300 and 390 nm, During the growth of the AlN cap, a thin cylindrical shell of AlN with thickness in few 10s of nms (decreasing thickness from top to bottom) is deposited on the sidewalls of the GaN nanopillar. The result of the patterned growth are subwavelength AlN phononic resonators that effectively ‘float’ above the substrate, supported by the dielectric GaN nanowire bases. We measure near normal incidence reflectance (±3.5°) of the nanowire arrays using a nitrogen-purged Bruker vertex 70 FTIR with an output beam collimated and reduced to ~ 6 mm through an external double-aperture. The reflectance data is compared to the reflection simulated with a corresponding TM-polarized 2-D model in COMSOL assuming a 20 nm thick uniform AlN shell around GaN nanopillar. In this work, we study representative data from the nanowires with diameter of 390 nm. The reflectance spectra show three prominent resonant dips. The longest wavelength features at 13.3 μm wavelength can be thought as a dipole mode at the top and bottom corner GaN/AlN interface. The next longest wavelength features at wavelengths λ = 12.3 μm corresponds to the LSPhR of the AlN caps that are confirmed via simulation of the nanowire structures. The LSPhR spectrally red-shifts with increasing nanowire diameters. Even more interesting is a sharp reflectance dip in AlN nanowires at wavelength, λ = 11.2 μm (AlN LO phonon energy). The fields at λ = 11.2 μm are calculated with 2-D COMSOL model, which indicate a strong field confinement in the AlN shell surrounding the GaN nanowire. While such a resonance would not typically be seen in a planar AlN film (or even a patterned AlN film) at normal incidence, the vertical orientation of the thin (~20 nm) AlN shell offers strong coupling to the Berreman mode. 1. L. Nordin et al. ... D. Wasserman. Applied Physics Letters, 111(9):091105, 2017. 2. M. Brubaker et al. … K. Bertness, Nanotechnology 30, 234001, 2019.

Localized Phonon Polariton Modes in GaN/AlN Nanowiresx

Dilute bismuth (Bi) incorporation in InGaBiAs is a promising material for extended short-wave infrared (e-SWIR, 1.7-2.5 μm wavelength) detection with a lattice match to InP-based materials. The InGaBiAs alloy is a highly mismatched semiconductor, where small concentrations of localized Bi states have a dramatic impact on the valence band electronic structure and the corresponding decrease in the bandgap energy. The use of InGaBiAs as an active material for e-SWIR photodetectors offers a means to overcome limitations of current approaches, including high dark current associated with relaxed InGaAs and low quantum efficiency of InGaAs/GaAsSb type-II superlattices on InP substrate. The epitaxial growth of InGaBiAs alloys has been previously demonstrated, with a bandgap energy shift of 56 meV/Bi% in InxGa1-xBiyAs1-y [1,2]. However, the details of optical absorption strength and minority carrier properties of key importance for photodetectors have not been explored in detail. In this work, the optical and electronic properties of InGaBiAs alloys and their relationship to epitaxial growth conditions will be reported. InGaBiAs materials were grown on InP at variable temperatures (265 and 490 °C) and V/III flux ratios. The growth parameters have a major influence on the tradeoff between efficient bismuth incorporation in the lattice and point defect density that influence the electronic properties of the material. The low temperatures (LT) grown samples are highly mismatched alloys with higher Bi incorporation. In the high temperatures (HT) grown samples, Bi acts as a surfactant. Optical absorption coefficient data were extracted from infrared transmission measurements, where the absorption edge was extended beyond 1.9 μm for Bi incorporation of 1.5% in comparison to an In0.53Ga0.47As reference sample while maintaining a high absorption coefficient (>104 cm-1) in the 1.5-1.85 μm spectral range. The minority carrier electronic properties have been investigated by temperature-dependent microwave-detected photoconductive decay (µ-PCD) measurements. For LT samples, µ-PCD measurements exhibit time constants less than 500 ns, corresponding to fast minority carrier recombination. Long-time constants of >100 µs are observed for the HT samples, which are attributed to carrier capture and re-emission from trap states with activation energies of 0.07 eV and 0.14 eV. The long photoconductive decay time constants are indicative of material with favorable minority carrier properties for photodetectors. Diode p-i-n junction devices incorporating InGaBiAs active layers were grown and fabricated into mesa devices using standard photolithography, chemical etching, and metallization processes. Dark current-voltage characteristics correlate with photoconductive decay measurements, where materials exhibiting long-time constants exhibit low dark current density (8.46x10-6 A/cm2) similar to InGaAs reference samples, while materials exhibiting short-time constants show high dark current density and/or significantly degraded diode rectification. Further development of InGaBiAs e-SWIR detectors will require a focus on co-optimization of bismuth incorporation and minority carrier properties, and continued exploration of optoelectronic device characterization. References: J. P. Petropoulos, Y. Zhong, and J. M. Zide, “Optical and electrical characterization of InGaBiAs for use as a mid-infrared optoelectronic material,” Applied Physics Letters, vol. 99, no. 3, p. 031110, 2011. R. Kudrawiec, J. Kopaczek, J. Misiewicz, J. P. Petropoulos, Y. Zhong, and J. M. Zide, “Contactless electroreflectance study of E0 and E0+Δso transitions in In0.53Ga0.47BixAs1−x alloys,” Applied Physics Letters, vol. 99, no. 25, p. 251906, 2011.

Prospects of Dilute Bismuth in InGaBiAs Alloys for e-SWIR Photodetectors

Diffusive memristors, also known as volatile electrochemical metallization memory cells (ECMs), are recognized as extremely interesting devices for various applications in emerging memories and neuromorphic computing areas. For non-volatile ECM cells, it has been shown that the counter-electrode (CE) material plays a crucial role in the switching process by affecting the reactions at the CE/electrolyte interface. This is due to the different electrocatalytic activity of the CE material towards reduction-oxidation reactions, which determines the metal ion concentration in the electrolyte and ultimately impacts the switching kinetics. In this work, we look at the switching behavior of diffusive memristors and how this is affected by different CE materials with a special focus on (i) the understanding of the influence of the CE material on the volatile switching process of diffusive memristors and (ii) device engineering and optimization towards industrially used and CMOS-compatible materials. To that end, we used inert Pt metal and two non-noble metals widely used in semiconductor technology, namely, W and TiN, as CE materials in Ag/HfO2/CE-based diffusive memristor cells. Rectangular voltage pulses of different amplitudes were applied and the SET times were analyzed from the transient curves. The results show that the CE material has a significant effect on the SET kinetics, with interesting differences being observed depending on the voltage regime. It is found that non-noble CE materials such as TiN and W form a native oxide either during ambient transfer or during the ALD process of the HfO2 electrolyte film. This has been confirmed by the XPS analysis of different stacks with and without the HfO2 layer. Furthermore, the formation of interfacial oxides at the CE/electrolyte interface in the case of non-noble metals is also discussed in relation to the observed differences in the SET kinetics. The findings of this work highlight the significant role of the CE material in the switching process of Ag/HfO2-based diffusive memristors and the importance of considering interfacial oxide formation in the design of these devices. This work was in part funded by the German Research Foundation (DFG) under Grant No. SFB 917, in part by the Federal Ministry of Education and Research (BMBF, Germany) in the project NEUROTEC (Project No. 16ME0398K) and NeuroSys (Project No. 03ZU1106AB) and are based on the Jülich Aachen Research Alliance (JARA-FIT).

Effect of the Counter Electrode Material on the SET Kinetics of Ag/HfO2-Based Diffusive Memristors

To overcome the von Neumann bottleneck and increase power efficiency in computation, neuromorphic computing has been considered which has the capability for parallel computing, long-term potentiation, and adaptive learning for developing energy efficient neural networks.1 Electric double layer (EDL) gated transistor uses ions within an electrolyte to induce high carrier density (1014 cm-2) in the channel, and its short term and long term ionic responses resemble a biological synapse, making it a promising platform for synaptic applications such as artificial synapses and neurons.2 The accuracy, computational demands, and simplicity of training neural networks depend significantly on a linear synaptic weight response (or plasticity), i.e. a proportionate synaptic weight update in response to input signals.3-6 However, achieving linear weight update in EDLT based synaptic devices have proven to be challenging with fixed magnitude input pulses.7-9 In this study, we first discussed the fundamental cause for nonlinear synaptic weight update in the aforementioned EDLT synaptic devices. With fixed magnitude input voltage pulses, while the amount of EDL build up during each pulse is constant, the amount of EDL dissipation in between pulses is dependent on the instantaneous EDL concentration and follows an exponential decay with respect to time. This leads to increasing amount of dissipation as pulses progress and EDL builds up nonlinearly. This behavior was confirmed with finite element modeling using modified Nernst-Poisson-Planck equations.10,11 A train of 10 pulses with frequencies ranging from 10 – 100 Hz (VG = 1 V) was applied to a parallel plate capacitor geometry consisting of PEO:LiClO4 as the electrolyte, and the ion concentration was calculated. As expected, the linear input pulses resulted in a non-linear response, where the maximum EDL concentration at 100 Hz eventually saturated at 9 x 1013 ions/cm2, more than 2 times smaller than the maximum EDL concentration at a steady 1 V (1.9 x 1014 ions/cm2). Then, we demonstrated that linear weight update can be achieved with varying input pulse widths and/or magnitudes (i.e., nonlinear inputs). A challenge for this approach is that the EDL concentration at the end of each pulse needs to be evaluated to predict the input voltage or width of the subsequent pulse. Based on the instantaneous change in EDL concentration with respect to time (dc/dt), we obtained an empirical relationship relating dc/dt, voltage, concentration, and time. Coupling this relation with the original COMSOL model, the input signals for a linear synaptic response can be predicted in a single computation. For a series of pulses with magnitude between 0.25 V and 3 V at a fixed frequency of 100 Hz, a linear synaptic weight update was obtained with R2 = 0.996. After 10 pulses the improved model resulted with a 13% increase in EDL concentration (to 1.02 x 1014 ions/cm2) and can continue to increase with subsequent pulses. These preliminary results provide insights into extending this model for an FET and developing an EDL gated synaptic network. As part of ongoing work, the group is currently working on experimentally demonstrating the model using parallel plate capacitors (metal-electrolyte-metal) and Graphene-based EDL transistors. 1. Schuman et al. arXiv abs/1705.06963, 2017; 2. Zhu et al. Adv. Mat., 2018, 30 (21); 3. Sung et al. Nanotech., 2018, 29 (11); 4. Lee at al. Adv. Fun. Mat., 2020, 30 (45); 5. Yang et al. Small Science, 2022, 2 (1); 6. Jacobs-Gedrim et al. IEEE (ICRC), 2017; 7. Jiang et al. Nanoscale, 2019, 11 (3); 8. Wan et al. Adv. Mat., 2016, 28; 9. Wen et al. ACS App. Mat. & Int., 2017, 9 (42); 10. Woeppel et al. ACS App. Mat. & Int., 2020, 12 (36); 11. Kilic et al. Phy. Rev., 2007, 75 (2)

Realizing a Linear Synaptic Weight Update in Electric-Double-Layer Gated Transistors for Achieving Spike-Timing-Dependent Plasticity in Neuromorphic Computing

A switching of resistive memory cells leads to a local accumulation of Joules heat in the device. In resistive RAM (ReRAM) arrays of memory cells, the heat generated in one cell spreads via common electrode metal lines to the neighboring cells and may cause their performance degradation. In our study, we used a baseline Cu/TaOx/Pt cell with a variety of alternative inert electrode cells replacing the inert Pt electrode. The performance degradation results in a reduced number of switching cycles and, in extreme cases, even in a loss of a bit, caused by the rupture of the nanofilament. We propose a thermal analysis of the thermal cross-talk, describe its impact on cells' electric performance, and identify three major mechanisms for the ReRAM reliability: (i) thermal conductivity, (ii) the specific heat capacity, and (iii) geometry of the electrodes. Several ReRAM arrays are manufactured to vary the thermal conductivity, specific heat, and geometry of the electrodes by depositing eight different inert electrodes: Pt(50 nm)/Ti(30 nm), Ru(50 nm)/Ti(30 nm), Co(50 nm)/Ti(30 nm), Pt(50 nm/Cu(100 nm)/Ti(30 nm), Pt(50 nm)/ Cu(200 nm)/Ti(30 nm), Ru(50 nm/Cr(30 nm), Ru(50 nm)/Ti(50 nm), and Rh(50 nm)/Cr(30 nm). The analysis handles the heat generation in nanostructures and its transfer to the nano-sized or micrometer-sized electrodes and how the heat transfer over the electrodes is transferred to nanofilaments of other memory cells sharing one common electrode. Using the proposed methodology, the experimentally found differences in the degradation of electric performance of the array cells performed under identical circumstances can be correctly predicted by the proposed thermal analysis using the material properties and geometry parameters of the electrodes. The analysis starts from the observation that the heat, Q, generated - typically between 3 μJ to 60 μJ - in a metallic nanofilament of a resistance Ron, - typically in the 1 kΩ to 100 kΩ range - if it were absorbed in the filament itself, it would lead according to the heat absorption equation of a body of mass m and specific heat capacity cs, Q=m×cs×ΔT, to a temperature higher than the temperature inside the sun of 2.7×107 oK. Temperature ΔT, this high is the result of the tiny volume of nanofilament of typically 5×10-18 cm-3. Since such a high temperature is impossible, the heat has to be accommodated in the ReRAM array otherwise, as it spreads to the more massive electrodes, depending on their mass (i.e. on their volume) and their specific heat capacity, and by the Newtonian losses which largely depend on the surface areas of the electrodes including the contact pads. Our analysis shows that the heat spreads across the electrodes w very quickly in the μs range due to the high thermal diffusivity, k, of the metallic electrodes. It can be shown that the typical time scale is given by τ=√(k×L), where L is e.g. the distance between two neighboring cells. Thus, within less than a second a steady state of temperature distribution is established resulting in linear dependence of the temperature distribution along the electrode when evaluating the heat conduction equation. The solution of the equation allows for determining the temperature of the passive neighboring cells when heated by an active memory cell. We have confirmed experimentally that the heat from the same heated filament spreads more efficiently and quickly along the Cu electrode than along the Pt electrode, caused by the thermal conductivity of Cu being 5.8 higher than that of Pt. In fact, we have confirmed experimentally that the reliability of the passive neighboring cells disposed along the Cy electrode is much worse than the reliability along the Pt electrode. The proposed thermal analysis allows predicting ReRAM critical switching voltages, the degradation of electrical performance, and the reliability of ReRAM devices contingent on the choice of the electrode materials and the total volume of the electrodes.

Methodology for Mitigation of the Reliability of a Resistive RAM Memory Array Caused by Thermal Cross-Talk Between the Memory Cells

Spin-orbit torque magnetic random-access memory (SOT-MRAM) has received extensive interest in the memory industry. Recent efforts have focused on a heavy metal (HM)/ferromagnet (FM) bilayer with an additional HM capping strip to deterministically switch the magnetization [1]. This paper investigates the switching behaviors of SOT-MRAM utilizing this structure with micromagnetic simulations coupled to the drift-diffusion spin transport model [2]. The three-dimensional spin transport solver self-consistently calculates the charge currents, spin currents, and spin accumulations for arbitrary geometries and multi-layer structures without importing a computed current density [2]. This work uses a simple W/CoFeB/MgO structure to realize deterministic magnetization switching based on the HM capping strip method, which can be readily adopted in magnetic tunnel junctions. Figure 1(c) shows the simulated structure. In the simulations, the FL magnetization starts from an initial state of Mz/Ms = +1. The pulse current density J is injected into the HM along the negative x-direction with a duration of 2 ns. After the pulse, the magnetization switches to the negative z-axis through the relaxation process. In a conventional HM/FM, there is no additional HM capping strip. The My/Ms approaches 0 and My/Ms approaches +1 after the current pulse, which leads to a non-deterministic state when the current is removed. However, Mz/Ms crosses over 0 and reaches a negative remnant value. After removing the current, Mz/Ms proceeds toward a downstate Mz/Ms=-1 and causes deterministic magnetization. We investigate the mechanism behind the HM-capping-strip-induced deterministic magnetization switching [2]. The spin accumulation distribution on the bottom HM interface is the key to understanding deterministic switching. With an HM strip capping on the HM layer, some non-negligible negative Sz is observed near the center y position, which is immediately above the FL. This negative Sz induces an additional negative z-direction spin torque when Mx/Ms=0, My/Ms=+1, and Mz/Ms=0 is reached. Therefore, a negative is observed under sufficiently large J. This is the critical factor of deterministic magnetization switching for the proposed structure. To understand the origin of this non-negligible Sz on the bottom HM interface, Figs. 3 show the origination from the negative z-direction spin on the edge of the HM capping strip. By characterizing the system with an accurate spin-flip length of tungsten, the drift-diffusion spin transport solver with a negative z spin on the edge of the HM capping strip leads to a non-negligible negative Sz on the bottom HM interface. Further, the spin accumulation along the y-axis on the bottom HM interface has an opposing polarity when applying the opposite direction of J. Thus, the magnetization switches from Mz/Ms = -1 to Mz/Ms = 1 by changing the polarity of the current. Mz/Ms reaches different under various J. This depends strongly on the current direction and magnitude, which indicates that deterministic bipolar switching can be achieved by changing the polarity of the current. A larger mr results in improved switching behaviors because it prevents the magnetization from stochastically switching under the interference of thermal fluctuations. Furthermore, Fig. 4(a) indicates that a larger mr induces a faster relaxation process when the current is removed, which gives a faster operating speed for the MRAM cell. Therefore, a larger current does not guarantee a higher switching speed. Instead, J with a magnitude slightly larger than Jc gives the ideal results. The relationship between Jc and w is also established, where Fig. 6(a) shows the SOT switching loops with different w. As w increases, Jc decreases. Instead of choosing the HM strip edge at the middle of the FL, the Jc minimum occurs near w=35 nm. [1] 35Y. Li, N. Zhang, and K. Wang, Sci. China Inf. Sci. 65, 122404 (2022) [2] S. Lepadatu, J. Appl. Phys. 128, 243902 (2020).

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