United States

Introduction: We report on the first demonstration of field emission characteristics of β-Ga2O3 nano-pillar arrays fabricated using a novel damage-free etching technique. The vacuum field emission characteristics of β- Ga2O3 is interesting due to its large theoretical breakdown field strength (8 MV/cm), high mechanical and chemical stability, and resistance to surface oxidation. The current literature on vacuum field emission of Ga2O3 is limited to a single nano-pillar fabricated using FIB [2] while β- Ga2O3 nanowires made using self-catalytic bottom-up processes display low threshold fields [3]. The β-Ga2O3 nano-pillar arrays were fabricated using an in situ Ga2O3 etching technique in an ultra-high vacuum environment to realize damage free, high aspect ratio nano-pillars with atomic scale etch precision. Electrically conductive Ga2O3 nano-pillars with sub-micron widths was realized without the use of e-beam lithography. Field emission characteristics on the nano-pillars displayed an emission current of 10 nA per tip at an electric field of 400 kV/cm. The field emission characteristics were modelled using the Murphy-Good model, and the measurements were validated with a field emission orthodoxy test. Experimental: A thin SiO2 sacrificial layer was deposited on a Sn doped (1×1018 cm-3) (010) β- Ga2O3 substrate as a hard mask for the in-situ etch. Circular arrays were patterned using a conventional photolithographic tool on the SiO2 layer. A portion of the patterned SiO2 layer was etched using an inductively coupled reactive ion etcher (ICP-RIE), and the remaining SiO2 was etched in diluted buffered oxide etch to prevent plasma damage to the Ga2O3 surface during the dry etch. The Ga2O3 etch was carried out at a chamber temperature of 700 oC and a Ga flux of 5x10-7 Torr for two hours which resulted in an etch depth of ~960 nm. Formation of nano-pillar arrays, ~240 in diameter was confirmed using a scanning electron micrograph. Results: The conductive nature of the fabricated nano-pillars was confirmed using conductive atomic force microscope measurements. Field emission characteristics were measured on a wafer with three Ga2O3 nano-pillar arrays (a total of 700 nano-pillars). The measurement was carried out in a vacuum chamber with a base pressure of ~6x10-8 Pa. The nano-pillar arrays displayed an emission turn-on field ~100 kV/cm, with a field emission current of 19 nA per tip at an applied field of 385 kV/cm. The Murphy-Good plot shows a linear relationship at high electric fields ranging from 250 kV/cm to 385 kV/cm. The field enhancement factor and the ‘fc’ value at each voltage were extracted based on the slope at the 1/V value. The orthodox pass dataset was calculated to be in the range, . The measurement data of β- Ga2O3 nano-pillar arrays were found to be within the range at high electric fields ranging from 250 kV/cm to 385 kV/cm. In summary, field emission characteristics of β- Ga2O3 nano-pillar arrays were demonstrated and modelled using Murphy-Good equation alongside independent validation using the orthodoxy test. We acknowledge funding from the Air Force Office of Scientific Research (AFOSR) through Award FA9550-19-0349 (Dr. Ken Goretta and John Lungisland). J. Ludwick was supported by the Air Force Research Labs under contract No. FA8650-16-D-5408. References: [1] Appl. Phys. Lett. 119, 123503 (2021). [2] Appl. Phys. Lett. 114, 193101 (2019). [3] J. Phys. D: Appl. Phys. 42, 185409 (2009).

EMC 2023

Demonstration of Gallium Oxide Nano-Pillar Field Emitter Arrays

field emitter array

field emission current

ga2o3

technical paper

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

EMC is coordinated with the Device Research Conference (DRC). This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. 

High Electron Mobility Transistors (HEMTs) are widely used in telecommunication, aerospace, and military for RF and power electronic applications1. High power operation of the AlGaN/GaN HEMT is significantly limited by self-heating effects caused due to inadequate heat extraction from the localized hotspot generated near high electron mobility channel 2. Unoptimized design for heat extraction and high thermal boundary resistance at the GaN/Substrate interface are the primary causes of poor heat extraction 3. Integration of diamond heat spreaders with high thermal conductivity has shown promising results in the thermal performance of the device4. However, several factors like GaN/Diamond thermal boundary resistance (TBR), optimal distance from the hotspot, and heat spreader configuration can lead to the sub-optimal thermal performance of the device. Consequently, in this work, we implement a multi-way heat extraction strategy for improving the thermal performance of the AlGaN/GaN/Diamond HEMT using a cohesive understanding of TBR and distance from hotspot to diamond heat dissipators. AlGaN/GaN HEMT with a GaN substrate (Fig 1a), is simulated to set a baseline performance, which showed a thermal resistance of ~80 K.mm/W (fig 2). Upon replacing the GaN substrate with a Single Crystalline Diamond at the bottom of the device (fig 1b), its thermal resistance reduced by ~13 times. Despite of remarkable performance improvements, the device still suffers at high power density due to low thermal conductivity of GaN layer and high TBR at GaN/SCD interface. Device with SCD at bottom operating at 40W/mm is simulated for varying values of GaN thickness (50 -2000 nm) and GaN/SCD TBR values (3.1-20 m2K/GW). Simulation output showed reducing GaN thickness provides a better heat extraction from the bottom of the device, however, only up to an optimum thickness, going thinner leads to higher device temperature (fig 3a). The optimum thickness has a positive correlation with GaN/SCD TBR, i.e., as the TBR value increases the GaN layer optimal thickness also increases. For very thin GaN layer, a steep increase of ~ 200K is recorded near the hotspot in the Lateral temperature profile of the device (Fig 3b), going from the edge of the device (~500 K) towards the hotspot (~700 K). This demonstrates as the thickness reduces heat in unable to spread in the GaN layer before reaching the thermal interface and increases the device temperature. Owing to 500 K temperature at the side edge, further enhancements to the device are made by adding Poly-Crystalline Diamond (PCD) side walls at the edge of the device (Fig 1c) along with SCD at the bottom. The device is simulated for the same GaN layer thicknesses and TBR values (Fig 4a). For the optimized value of GaN layer (200 nm) and lowest TBR (3.1 m2K/GW) a significant drop of ~ 150 K is observed in the device temperature due to 3-way heat extraction. Lateral temperature profile (fig 4b) recorded ~330 K at GaN/PCD-sidewall interface and ~550 K at the hotspot which still showed a steep rise of ~200K, which illustrates that, lateral thermal resistance of GaN layer limits maximum heat extraction plausible from the edge of the device. Therefore, to extract heat from the hotspot region, an additional PCD layer with associated interface TBR layer is added on top of the device. The additional heat extraction path led to a temperature reduction of 70 K. Consequently, using side, top, and bottom heat extraction pathways and optimization of GaN layer in correlation with TBR, an AlGaN/GaN HEMT operating at a power density of 40W/mm are simulated with temperature ~470-500 K. [1] Fletcher, A. Superlattices and Microstructures vol. 109 519–537 (2017). [2] Gaska, R. et al. IEEE ELECTRON DEVICE LETTERS vol. 18 (1997) [3] Chen, G. PhD. et. al. Annual review of heat transfer. Volume 18 [4] Jessen, G. H. et al. IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC 271–274 (2006)

Understanding of Multi-Way Heat Extraction Using Peripheral Diamond in AlGaN/GaN HEMT by Electrothermal Simulations

Gallium nitride (GaN) MOSCAPs and MOSFETs are often investigated for high-power applications ranging from electric vehicles to photovoltaic invertors and smart electric grids. The specific material properties of GaN, including its wide bandgap, higher obtainable breakdown voltages, and higher electron mobilities, enable novel advantages not attainable using traditional silicon power devices. Among the many challenges reported for vertical GaN MOSFETs, optimization of the semiconductor/dielectric interface is crucial to improve important parameters such as threshold voltage, leakage currents, and interface trap densities (DIT). Previous work on GaAs has shown the importance of GaxOy mitigation through sequenced TMA purging for improved interfaces but has not elaborated on the impact of this on electrical output characteristics. For GaN, to date little work has been published that analyzes the impact of minimized interfacial GaxOy from optimized ALD techniques and its effect on electrical performance in MOS devices. Minimizing GaxOy formation at the semiconductor-dielectric interface is necessary to obtain optimal performance in GaN MOS structures. The fundamental understanding of the impact of improved oxide deposition techniques for GaN MOSFET gates is critical to accurately describe device performance. Relative improvements to dielectric leakage, DIT distributions, and capacitance-voltage (C-V) trends may be analyzed to understand how each is affected through the elimination of native oxide concentrations at the interface of GaN MOSFET gates. This study analyzes changes in electrical performance of Al2O3 dielectrics fabricated using atomic layer deposition (ALD) techniques on GaN epilayers grown on bulk GaN substrates (GaN-on-GaN). Traditional ALD deposition techniques for aluminum oxide (Al2O3) utilize reactions of trimethyl aluminum (TMA) and water to form dielectric films on various substrates. Previous studies have shown that gallium oxide (GaxOy) formation on gallium arsenide (GaAs) can be alleviated by cycling TMA purges during ALD deposition to control oxidation states and mitigate Ga-O and As-O bonding. For GaN, improvements to gate interfaces of high-k dielectrics such as Al2O3 are crucial to ensure optimal switching and electrical response of complex vertical GaN MOSFETs. Leakage currents and high densities of interfacial traps have been shown to reduce device performance in previous studies. This work shows improved C-V responses of ALD Al2O3 films using quasi-static capacitance measurements. Optimized films were fabricated by the mitigation of GaxOy at the semiconductor/dielectric interface. Films grown on substrates that did not receive a TMA dose prior to the H2O precursor for ALD growth of Al2O3 films show a significantly higher amount of native oxide between the semiconductor and gate dielectric. The relative percentage of native oxide found at the interface is quantified via x-ray photoelectron spectroscopy (XPS) and shows a significant reduction following TMA purges. This improved ALD technique for Al2O3 deposition also shows a reduction of mid-gap trap states and hysteresis observed during C-V testing which further indicates improved interface quality and electrical response of the tested devices. Relative improvement to film quality is dependent upon improved gate dielectric deposition techniques which diminish GaxOy concentration at the semiconductor/dielectric interface. The impact of gate interfaces on GaN MOS devices is directly linked to calculated DIT, leakage currents, and other important electrical characteristics which must be optimized on simple device structures prior to implementation in complex architectures such as vertical GaN MOSFETs.

Improving Electrical Performance of GaN-on-GaN MOS Devices Via Optimized Atomic Layer Deposition of Al2O3 Gate Dielectrics

Wide bandgap GaN holds great promises for high-efficiency power conversion systems. To realize GaN power integrated circuits (ICs), peripheral logic circuits based on GaN are necessary, such as controllers, drivers, protection circuits. By using the AlGaN/GaN high electron mobility transistors (HEMTs) platform, all these components can be integrated on a single chip, dramatically reducing parasitic effects, such as gate ringing and false turn-on of power transistors. Currently, most GaN logic circuits still rely on only n-channel devices. This is because it is challenging to realize high-performance GaN p-channel devices due to much lower hole mobilities and sheet carrier density. Recently, multi-channel heterostructure is proposed to address the tradeoff between carrier mobility and density. But there are still few reports on GaN multi-channel p-type devices partly due to the difficulty in buried p-GaN activation, unknown doping concentration and thickness of the inserted p-GaN layers, and the acceptor-holes separation process. In this work, we perform the design, modeling and fabrication of GaN-based vertically stacked 2DHG (two-dimensional hole gas) multiple p-channel Schottky barrier diodes (SBDs). The schematic of cross-section of an SBD with 5 2DHG-channels is shown in Fig. 1(a), and the energy band structure from the cutline is shown in Fig. 1(b). The device epilayers were grown by metal-organic chemical vapor deposition (MOCVD) on a sapphire substrate, consisting of a thick GaN buffer layer, a 300 nm UID-GaN layer, and multiple layers for p-channels that are composed of a 40 nm p+-GaN layer, a 20 nm UID-GaN layer, and a 15 nm Al0.2Ga0.8N layer. In order to effectively activate the buried p-GaN layers, trenches with different geometric patterns between the anode and cathode were etched by 400 nm of depth. The devices were then annealed at 800 °C for 1 hour to break the Mg-H bond and allowed the [H] to diffuse to the ambient through the etched sidewall. Moreover, these trenches are also geometrically designed as edge terminations that can eliminate high electric field crowding at reverse bias, which is necessary due to the vulnerability of the etched trenches, as shown in Fig. 2. Finally, the two electrodes and passivation layer were deposited on top of the devices. The distance between the anode and the cathode is from 15 um to 25 um. For the simulation, the impacts of doping concentration and thickness of p-GaN layers and the thickness of UID-GaN layers of the multi-channel heterostructure will be comprehensively investigated. And the ionization energy of [Mg] in GaN was set to be 300 mV. For the forward performance, as shown in Fig. 3(a), the ON-current densities at an anode voltage of －3.5 V for the SBDs with 1, 3, and 5 p-channels were extracted as 0.12, 0.26, and 0.365 mA/mm, respectively. With the thickness of each UID-GaN between p-GaN and AlGaN increasing from 2 to 5, 10, and 20 nm, as shown in Fig. 3(b), the ON-current is also increased from 0.24 to 0.265, 0.3, and 0.365 mA/mm. For the fabrication, as shown in Fig. 4(a) and 4(b), the SBD with 1 2DHG channel and 3 2DEG channels with different doping concentration in p-GaN layers have been fabricated. Compared with the SBD with 1 channel, the SBD with 3 channels and higher concentrations of doping in p-GaN layers has larger current. The performance of these devices needs to be further optimized during the following work. These results can provide critical references for the future development of GaN multiple p-channel devices such as multiple p-channel diodes and FETs for integrated power and logic circuits.

Design and Fabrication of AlGaN/GaN Multiple P-Channel Schottky Barrier Diodes

Gallium Nitride (GaN) is a promising wide bandgap (~3.4eV), material for high-power electronics. GaN devices can sustain a high breakdown voltage (BV) and high temperature operation, providing faster switching frequencies with lower power losses. Compared to lateral devices, vertical rectifiers have larger breakdown voltages and operate in a vertical depletion mode which can mitigate surface breakdown problems. Our prior work has demonstrated that nitrogen-implanted floating guard rings (FGRs) can serve as an effective edge termination technique, as uniform average reverse breakdown above 1.2kV and low turn-on voltage of 3.5V can be achieved. However, even though GaN device technology has made significant advances, remaining material defects have a detrimental impact on device performance. In this study, photoluminescence (PL) imaging was performed after growth and prior to the device processing to evaluate the impact of material quality on the fabricated PIN rectifier performance. Epitaxial growth on the GaN face of a (0001) ammono-thermally grown bulk GaN substrate was performed in an AXITRON metalorganic chemical vapor deposition reactor equipped with a close coupled showerhead. The device structure consisted of a 0.5μm n-GaN:Si ([n]=6×1018 cm-3), 8.5μm GaN:uid drift layer, a 450nm p-GaN:Mg ([p]=1×1018cm-3), and a 20nm p+-GaN:Mg ([Mg]=1×1020cm-3). The device fabrication started with the deposition of Ni/Ag/Ni/Au or Ni/Ag/Pt p-GaN ohmic contacts, followed by annealing in dry air for ohmic contact formation. Three-step ion implantation with nitrogen forms the highly resistive device isolation regions as well as the FGR structures in the p-GaN layer. Prior to implantation, TCAD simulation was performed to determine the optimum FGR, i.e., widths of 4μm and gaps of 2μm, in order to prevent premature device breakdown and achieve a smooth potential profile along the device surface under reverse bias. After ion implantation, the backside Ti/Al/Ni/Au n-metal contact was formed without annealing. The J-V characteristics of two batches of devices on separate GaN wafers, namely sample A and B, were each measured at 300K with 400 devices within a 1cm×1cm block region consisting of two device groups with mesa diameters of 100μm and 200μm. Sample A had an overall average BV of 1209±229V at 0.01A/cm2, with 274 out of 400 (68.5%) measured devices reach BV>1.2kV. The average BVs were 1228±190V and 1190±261V for 100μm and 200μm diameter devices on sample A, respectively. Sample B had an overall average BV of 1095V±210V at 0.01A/cm2, with 241 out of 400 (60.25%) measured devices able to reach BV>1.2kV. The average BVs were 1156±163V and 1033±233V for 100μm and 200μm diameter devices on sample B, respectively. The distribution of measured BV’s as well as the PL image on macro-scale of the measured blocks show a correlation between low BV devices and Mg concentration non-uniformity. The lower PL intensities are related to higher Mg doping concentrations. This is because the PL emission of donor-acceptor pair recombination is suppressed in heavily doped GaN:Mg layers. From the high-resolution PL scanning, it is found that a variety of macro-defects in GaN epi layer, such as cracks, triangular hillocks, particles, and surface roughness induced by step bunching contribute to the increased leakage current density and lower BV of the devices. Dislocations appearing as dot features with dark cores and bright light rings are also observed in PL imaging, and their impact on device performance will be discussed. Acknowledgements This work was performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344. R. D. Dupuis acknowledges the support of the Steve W. Chaddick Endowed Chair in Optoelectronics. This work was in part performed in facility supported by the National Nanotechnology Coordinated Infrastructure (NSF Grant ECCS-154217).

1.2kV Vertical GaN PIN Rectifiers with Nitrogen-Implanted Floating Guard Rings as Edge Termination and Breakdown Characteristics Correlation Study by Wafer-Level Photoluminescence Mapping

Aluminum nitride (AlN) is considered a future candidate for the future power electronics applications for its wide bandgap (6.2 eV), high thermal conductivity (340 W/mK), and high breakdown field (~12 MV/cm). However, due to the challenges in material growth and device fabrication, very limited work has been reported on AlN electronics, and the full potential of AlN material is yet to be discovered. The impact ionization (II) coefficients, which determine the blocking limits of AlN power devices is still both experimentally and theoretically imprecise but is under study at present. Here we collected the different II coefficients reported in the literature and analyzed their impacts on the device performance with TCAD Silvaco. The quasi-vertical AlN Schottky diode is simulated in Silvaco TCAD environment. Selberherr’s II model is employed to analyze the breakdown performance of the device as: αn,p=an,pexp(-bn,p/E) Where α is the II coefficients, E is the electric field, and a, b are the parameters need to be determined. 3 II coefficients are collected from the theoretical results reported, which have a large discrepancy: one calculated from the full-band Monte Carlo model in E. Bellotti et al. [1], one calculated from the ensemble Monte Carlo framework in C. Bulutay et al. [2], and one in N. Lophitis et al. [3]. and another one coefficient is determined by calibration to have a breakdown field of 12 MV/cm. The drift region thickness (W) is set to be 1 mm and the N-type doping concertation (Nd) is set to be 1017 /cm3. A 100 nm SiO2 passivation is employed to optimize the blocking capabilities. The 4 coefficients are applied to the model and their impact on the device performance are analyzed with the simulation. The breakdown voltages (BV) for the 4 II coefficients are 351, 355, 2090, and 527 V respectively. The discrepancy of the II coefficients also affects the electric field distribution while the breakdown fields for the 4 II coefficients are 8.8, 8.8, 43, and 12 MV/cm respectively. The distribution of the electric field in the devices shows the breakdown occurs due to EF crowding at the anode edge, however, it is alleviated by SiO2 passivation structure. [1] J. Appl. Phys. 111, 103711 (2012). [2] Semicond. Sci. Technol. 17, L59 (2002) [3] Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications. (2018)

Effect of Impact Ionization Coefficients on High-Voltage Vertical AlN Power Devices

Lateral epitaxial overgrowth (LEO) enables lithographically patterned dielectric features to be embedded within single-crystal semiconductor materials. InP-based photonic crystal surface-emitting lasers (PCSELs) take advantage of the index contrast created by periodic arrays of encapsulated voids while avoiding the challenges of growing distributed Bragg reflectors at this lattice constant [1]. LEO on photonic crystals (e.g., arrays of triangles) requires coalescence from multiple crystal fronts, which can introduce pits, as well as threading dislocations (TDs) and stacking faults (SFs) [2]. In this work, we demonstrate selective InP nucleation and coalescence on patterned InP substrates with designed feature sizes of 266-1110 nm by solid-source molecular beam epitaxy (SS-MBE). Despite the lack of lattice mismatch, we find that extended defects form before the completion of coalescence in all cases and that LEO on smaller features with sides aligned away from [0 -1 1] and [0 1 1] directions favors lower defect densities. InP substrate patterning started with 40 nm of SiN deposited by PECVD and patterned by e-beam lithography. Reactive ion etching left arrays of SiN isosceles-right triangles with side lengths of 465-1110 nm and polygons with a side length of 266 nm. The sides of the triangles were aligned along [0 -1 1] and [0 1 1] crystallographic directions, while the sides of the polygons spanned a wide range of directions. We found a pre-growth cleaning procedure consisting of O2 plasma ashing and wet cleaning in uncut (98 wt%) H2SO4 to enable InP surface morphologies matching those on epi-ready wafers. Samples consisting of 20 and 350 nm of Be-doped InP (1018 cm-3) were grown on patterned n-InP at an elevated substrate temperature (Tsub) of 500°C and a low growth rate of 0.2 μm/hr to encourage selectivity [3]. Thicker samples of 1300 nm p-InP were initiated using the same conditions for the first 500 nm, followed by a second growth step at more typical InP MBE growth conditions of 440°C, 1 µm/hr. InP growths of 20 and 350 nm at Tsub = 500°C show good selectivity, as no polycrystalline nucleation was found on the dielectric regions. After 350 nm of growth, coalescence was completed over the 266 nm polygons, while an array of small pits was observed over the 1110 nm triangles. After 1300 nm growth, the InP surface was fully coalesced, regardless of feature size, with small, enclosed voids above the SiN patterns. Despite the excellent selectivity, we have found that Tsub = 500°C leads to rough InP surfaces, and the rms roughness of the coalesced films was ~30 nm due to high densities of hillocks. Using electron channeling contrast imaging (ECCI), we find that InP LEO on the 266 nm polygons shows the lowest density of extended defects. 1300 nm overgrown InP on the 266 nm polygons had a TDD of 5.0 × 106 cm-2, which is an order of magnitude lower than on the 465 and 1110 nm triangle patterns. Stacking fault density (SFD) decreases by nearly 10× as the feature size decreases from 1110 to 266 nm. At a pattern size of 1110 nm, ECCI reveals an unexpectedly asymmetric distribution of SFs with [0 -1 1]-oriented SFs over every buried triangle and virtually no [0 1 1]-oriented SFs. Consistent with the ECCI results, we find that overgrown InP on 266 nm polygonal patterns exhibits 3.9 and 1.6× greater photoluminescence intensity than on 465 and 1110 nm patterns, respectively. Future work will focus on reducing surface roughness while maintaining selectivity and on better understanding the effect of pattern geometry on the formation of extended defects. References [1] K. Hirose, Y. Liang, Y. Kurosaka, A. Watanabe, T. Sugiyama and S. Noda, Nat. Photon 8, 406–411 (2014) [2] D. J. Ironside, A. M. Skipper, A. M.García and S. R. Bank, Prog. Quantum. Electron. 77, 110316 (2021) [3] M. Fahed, L. Desplanque, C. Coinon, D. Troadec and X. Wallart, Nanotechnology 26, 295301 (2015)

InP Lateral Epitaxial Overgrowth by Solid-Source Molecular Beam Epitaxy

Magnetic topological insulator could achieve quantum anomalous Hall (QAH) effect and spin-orbit torque (SOT) switching in the same structure. This is promising for its future applications in memory or switching applications with its robust surface properties by topological protection. In this work we have grown Cr:(BixSb1-x)2Te3 and MnBi2Te4 on GaAs (111) substrate through modulation doping by MBE (Molecular Beam Epitaxy). The doping level and the thickness of each layer is examined to tune the bandgap and the Fermi level of the whole sample. In this way, we can tune the Fermi level into the bandgap and optimize the total resistivity to achieve quantization. Considering the van der Waals nature of the epitaxial layers, it has very weak van der Waals bonding with the substrate. This gives rise to a quasi Van der Waals epitaxial growth mode at the interface of GaAs (111) and epitaxial layers. In this growth mode strain relaxes quickly within the 1st epitaxial layer. Growth mechanism and the influence on its transport properties are also discussed.

Quasi Van der Waals Epitaxy of Magnetic Topological Insulator on a GaAs (111) Substrate

Bismuth (Bi)-containing III-V semiconductor materials are attracting considerable interest due to their predicted non-trivial topological surface states and band inversion. These topological surface states (TSSs) have their spin locked with orbital momentum because of large spin-orbit coupling, presenting the high charge to spin conversion efficiency and application in spintronics. [1, 2] Previously, either Bi1-xSbx bulk growth was studied, [3] which is hampered by low Bi incorporation, or the focus was set on the growth of metallic Bi films on top of semiconductor substrates, [4] without highlighting the Bi-substrate interaction. However, it is vital to experimentally investigate the Bi-semiconductor interface and the potential formation of Bi-induced topological surface states, not just for spintronics application but also from the fundamental physics point of view. Here, we investigate the incorporation of Bi atoms into the semiconductor surface, thus increasing the local Bi content in the semiconductor and forming atomic-scale heterostructures in a controlled way. We will present multiple steps of Bi incorporation in the InSb(111)B surface using a combined study of scanning tunneling microscopy (STM), X-ray photoemission spectroscopy (XPS), and low energy electron diffraction (LEED). After cleaning the InSb(111)B surface from native oxide using atomic hydrogen, STM shows a 3X3 reconstruction, in agreement with previous studies. [5] We observe that Bi incorporation on a heated InSb(111)B substrate (Ts=250 C) initiates by forming a buckled triangular atomic arrangement. XPS of the Bi 5d core-level shows that Bi interacts with Sb by forming Bi-Sb bonds. Interestingly, the incorporation is self-limiting, i.e., the amount of Bi in a Bi-Sb configuration remains unchanged irrespective of deposition cycles for the heated sample. Further deposition of Bi at room temperature (RT) instead results in multi-layer thick Sierpinski-type defective triangles [6] comprising mainly metallic Bi. However, the Bi incorporation under the before-mentioned conditions occurs predominantly at random sites on the surface, hindering the formation of a large-scale symmetric surface layer. However, when Bi was deposited at RT, followed by an annealing step at 250 C for 15 minutes, a periodic (2X2) reconstructed surface was observed. XPS indicates that also this ordered 2X2 surface is characterized by Sb-Bi bonding, similar to the chemical state of the surface that results from Bi deposition at Ts=250 C (as mentioned above). Similar 2X2 reconstruction can be obtained if the sample is annealed (at Ts= 250 C) in-between any Bi deposition conditions. That shows that Bi bonded to Sb tends to stabilize in a 2X2 periodic surface structure of self-limiting bonding configuration. In summary, we present the formation of a controllable and ordered, atomically thin Bi-Sb layer on InSb which is highly promising for realizing 2D topological insulators on III-V semiconductor substrates. References: [1] S. Fragkos et al., Phys. Rev. Materials 5, 014203 (2021) [2] T. Campos et al., Phys. Rev. B 97, 245402 (2018) [3] D. Hsieh et al., Nature 452, 970 (2008) [4] Z. Liu, et al., Phys. Rev. Lett. 107, 136805 (2011) [5] J. Wever et al., Surf. Sci., 321, L225 (1994) [6] C. Liu et al., Phys. Rev. Lett., 126, 176102 (2021)

Self-Limiting Formation of Bismuth-Induced Nanostructures on the InSb(111) Surface

The 2D TMD-based thin film materials have been believed to be a potential candidate for replacing the Si CMOS technology. Ideally, the 2D material has better device scaling and interface properties. However, contact resistance has been a big issue in the transistor's design due to the difficulties in material doping. It is difficult to dope in 2D material in the contact region to reduce the contact resistance and form an ohmic contact. Hence, most of the work is to find a good metal to adjust the work function. For nMOSFET, a smaller work function material is needed, and a high work function metal is needed for p-MOS. In this work, a new CFET design based on 2D Janus MoSSe material has been proposed based on the polarization field induced by the asymmetric structure. The 2D Janus MoSSe material has been found to have a strong polarization field, which is even larger than the nitride-based polar material because the structure is asymmetric. The p-type and n-type ohmic contact can be formed at the opposite surface by utilizing the asymmetry polarization property of the two opposite surfaces. The positive polar charge surface will attract electrons to form a 2DEG at the surface and make the n-type ohmic contact. The negative polar charge surface will attract holes to form a 2DHG and a p-type ohmic contact. Based on these properties, the n- and p-FET can be produced without doping; combined into a CFET by symmetric structure. In our DFT calculation, the dipole fields are up to 106 V/cm order (Table 1) for both MoSSe and WSSe. The DFT calculated projected band structures of 1 and 2-layer-MoSSe/graphene systems with different side contact are calculated to show the p- and n-type contact formation (Fig.1). If graphene makes contact with the Se-side, the 0.2 eV N-type Schottky barrier is formed. And yet, if graphene makes contact with the S-side, we see a 0.3 eV P-type Schottky barrier. In the 2-layer MoSSe case, we find that the N-type barrier for S-side contact is reduced to 0.1 eV, and the Se-side achieves p-type ohmic contact. The intrinsic dipole-induced p- and n-type ohmic contact can also be formed at the metal/MoSSe interface. The DFT extracted data, such as spontaneous polarization and thickness, are further put into the 2D finite difference Poission-Schrödinger solver developed by our lab to design the transistor. Similar to the GaN HEMT devices, this intrinsic dipole in MoSSe material causes band bending, producing 2DEG and 2DHG at the interface region (Fig.2). Thus, the p-FET and n-FET structures are constructed by placing a channel region between two Metal/MoSSe interfaces through attaching contacts to the different faces of JTMD. Then combining p- and n-FET, the CFET structure can be fabricated using a single film. Based on the above-mentioned property, we design the p- and n-FET structure shown in Fig.3 and Fig. 4 and perform the simulation. The double gate structures are used to have better control of the channel. To make the enhanced mode of operation, the HfO2 material was chosen as the gate dielectrics. The device achieves a smaller SS value (~61 mV/dec) (Fig.5 and Fig. 6). Fig. 7 is the majority carrier density plot with different gate biases, the switching between on and off states can be observed. Furthermore, to make the device fabrication process realistic, we proposed a structure that could be built layer by layer (Fig.8). Based on the I-V curve obtained from the 2D simulation result, we built the model and further performed the circuit simulation by LTspice (Fig.9). Set VDD equals to 1.5V, and the middle plot is Vin to Vout of the CMOS inverter. The JTMD materials have a similar transport property as MoS2 and WS2. With the built-in polarization field and a proper design, it is possible to make CFET devices in a single thin film without doping.

Surface Polarization Engineering Design of 2D Janus MoSSe Complementary Field Effect Transistors

We report our initial results on the fabrication and characterization of 2D materials/III-As semiconductors heterostructures in a planar and helical geometry. These materials promise to support the generation of cyclotron THz radiation with technologically relevant levels of power density (i.e., between 100s mW/cm2 and few W/cm2) under an applied DC bias. An intuitive approach based on a time-of-flight and interference argument shows that radiation frequencies in the THz range are expected from helices with a radius ranging from a few tens to a few hundred nanometers. The exceptional compliance of 2D materials allows them to bend with nanoscale radius curvature without any plastic deformation. A 2D material with high carrier mobility is also required to limit carrier scattering within the helices and thus reduce spectral broadening around the center frequency. h-BN/graphene/h-BN heterostructures will potentially satisfy all the desired attributes to generate cyclotron radiation based on previously reported values of carrier mobility. We create the helical ribbons via guided self-assembly of graphene-based/GaAs/InxGa1-xAs heterostructures with a thickness of ~2-20 nm. This process enables the fabrication of nanoscale-diameter structures whose dimensions can be precisely manipulated in that they depend on residual strain in a nanosheet, its stiffness, and its geometry in the plane perpendicular to its thickness. These are all parameters that can be readily controlled via top-down processing techniques. In our work, multi-layer stacks comprising a GaAs/InxGa1-xAs bilayer and an AlAs sacrificial layer are deposited by molecular beam epitaxy on a (001) GaAs substrate surface. Materials combinations and growth conditions are appropriately selected to establish a large strain gradient across the thickness of the III-As bilayer. We then fabricate h-BN/graphene/h-BN heterostructures on the semiconductor bilayer via polymer-assisted release, transfer of the 2D materials, and vacuum annealing in Ar atmosphere to remove the polymer support. X-ray photoelectron spectroscopy characterizes the removal of the polymer during annealing. Next, the 2D materials/GaAs/InxGa1-xAs nanosheets is patterned into ribbons at a non-zero angle with the softest crystallographic direction in GaAs. Selective etching of the AlAs sacrificial layer results in the nanosheet bending and twisting towards the softest crystal direction (i.e., <100>). We have fabricated structures with a scalable diameter between 30 nm and 800 nm, as estimated by scanning electron microscopy. In addition to illustrating the controlled synthesis of graphene helical ribbons, we present magnetotransport and multi-carrier analysis techniques to characterize mobilities and carrier concentrations in the fabricated heterostructures. A precise knowledge of these parameters will improve our predictive capability of the electromagnetic radiation originated by accelerated charges along the helical path. We fabricate graphene-based/GaAs/InxGa1-xAs Hall bar devices on AlAs-coated substrates and perform variable temperature magnetotransport on a Quantum Design Magnetic Properties Measurement System (MPMS). Multi-carrier analysis techniques are used to shed light on the dominant carrier scattering mechanisms and surface transfer doping of encapsulated graphene on III-As nanosheets. ACKNOWLEDGEMENT. This work was supported by the U.S. AFOSR/Clarkson Aerospace Corporation through award No. FA9550-21-1-0460/UNM 21-1-0460.

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