United States

Several different designs of 1.2kV-rated 4HSiC JBS diode integrated MOSFETs (JBSFETs) have been successfully fabricated to increase the 3rd quadrant device performance while maintaining the electrical characteristics on both the forward and blocking modes of operation when compared to its MOSFET counterpart. Incorporating the Schottky area in an efficient manner to improve overall device performance has been a critical path in the development and adoption of 4H-SiC JBSFETs rather than MOSFETs copackaged with JBS Diodes. Device design, fabrication, and electrical performances are discussed in this paper and as a result, an optimum JBSFET design is proposed.

IEEE WiPDA 2022

Exploring Optimum Designs for 1.2kV 4HSiC JBS Diode Integrated MOSFETs (JBSFETs)

leakage current

design approach

3rd quadrant

junction barrier schottky diode

4h-silicon carbide (sic)

jbsfet

mosfet

breakdown voltage

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
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* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
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JOINT PLENARY talks live broadcast: September 13, 2021 
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Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

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 The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.
 
 **Topics of interest**
* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency Or Compact Converters
* Safe Operating Areas Of Wide Bandgap Devices, including Short Circuit, Spike, &Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Hard-Switched & Soft-Switched Application Analysis
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, Grid Power Systems, Space and Aerospace
* Wide Bandgap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging

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The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

In this paper, we explore the optimization of “saddle” type finger layout for lateral SiC RESURF (Reduced Surface Electric Field) diodes where concave/convex finger ends combined with mesa etch isolation achieve over 82% of the inner cell breakdown voltage. Furthermore, added deep P+ JBS pattern near the anode Schottky contact significantly improves robustness against field crowding when cell pitch/finger width is reduced to densify the chip. Improved surge current capability compared with pure Schottky structure is investigated through mix-mode TCAD simulation. The proposed design methodologies offer guidance for future efforts toward realizing a monolithic SiC high voltage integrated circuit.

Design Optimization and Surge Current Capability of 4H-SiC Lateral Deep P+ JBS Diode on Thin RESURF Layer

It is well known that the high density of interface traps (Dit) near the conduction band (CB) edge limits the net inversion layer charge in the conduction band of a 4H-SiC/SiO2 MOSFET in strong inversion. Measurements at cryogenic temperatures are necessary to study the presence of interface trap density (Dit) up to the CB edge. In our study, we extracted the threshold voltage (VT) from cryogenic (10 K) to high temperature (500 K) and calculated the VT shift which is a measure of interface trapped negative charge (∆Qit). This shift in negative charge is used to estimate a relative magnitude of Dit near the CB edge. The higher the value of ∆VT, the higher the Dit for a given sample.

Characterization of Near Conduction Band SiC/SiO2 Interface Traps in Commercial 4H-SiC Power MOSFETs

In order to evaluate the time evolution of avalanche breakdown in wide and ultra-wide bandgap devices, we have developed a cable pulser experimental setup that can evaluate the time-evolution of the terminating impedance for a semiconductor device with a time resolution of 130 ps. We have utilized this pulser setup to evaluate the time-to-breakdown of vertical Gallium Nitride and Silicon Carbide diodes for possible use as protection elements in the electrical grid against fast transient voltage pulses (such as those induced by an electromagnetic pulse event). We have found that the Gallium Nitride device demonstrated faster dynamics compared to the Silicon Carbide device, achieving 90% conduction within 1.37 ns compared to the SiC device response time of 2.98 ns. While the Gallium Nitride device did not demonstrate significant dependence of breakdown time with applied voltage, the Silicon Carbide device breakdown time was strongly dependent on applied voltage, ranging from a value of 2.97 ns at 1.33 kV to 0.78 ns at 2.6 kV. The fast response time (< 5 ns) of both the Gallium Nitride and Silicon Carbide devices indicate that both materials systems could meet the stringent response time requirements and may be appropriate for implementation as protection elements against electromagnetic pulse transients.

Reverse Breakdown Time of Wide Bandgap Diodes

We investigate the drift of threshold voltage (VTH) and on-resistance (RON) in p-GaN power HEMTs after being submitted to negative/positive gate stress. Negative (Positive) Gate Stress (NGS/PGS) was applied at a gate-to-source bias of |VNGS| = VPGS = 6 V up to a cumulative stress time of 8×103 s at room temperature. We found that during NGS both VTH and RON increased over stress time, whereas during PGS both parameters decreased and stabilized to the values prior to stress application. This symmetric behavior was maintained after 5 full NGS/PGS stress cycles, indicating the absence of permanent degradation. To further characterize the VTH and RON transients, the NGS/PGS stress cycles were repeated at different temperatures (T=30-105 °C). While VTH exhibited a strong Tdependence (EA ≈ 0.6 eV) during NGS, a negligible variation of the VTH transients with T was found during PGS (EA ≈ 0 eV). Instead, RON transients exhibited approximately the same Tdependence during both NGS and PGS (EA ≈ 0.3-0.4 eV).

Symmetrical VTH/RON Drifts Due to Negative/Positive Gate Stress in p-GaN Power HEMTs

Reliability tests are a decisive step for GaN technology qualification. To evaluate the Mean Time to Failure (MTTF), it is necessary to know well the peak channel temperature (Tpeak) reached at the hottest point of the device. For an AlGaN/GaN High Electron Mobility Transistor (HEMT), this region lies at AlGaN/GaN interface where the two-dimensional electron gas (2DEG) is located near the gate contact. InfraRed (IR) Thermography was performed on our GaN on Si HEMT devices to measure Tpeak. Considering the correction in underestimation of Tpeak temperature, the MTTF was extracted. We also performed Raman measurements and Tpeak was evaluated with the aid of 3-Dimensional thermal simulations. The Tpeak difference between IR and Raman technique is more than 100°C and far from the evaluation of about 40-50°C often found in literature. The reliability measurements show a high robustness and from the Raman approach MTTF is approximately 109 hours instead of the 106 hours estimated with the IR method at Tpeak =200°C.

Peak Channel Temperature Determination for an AlGaN/GaN HEMT with Raman Thermography and MTTF Extraction for Long Term Reliability

This paper reports on the high temperature (HT) robustness of enhancement-mode (E-mode) p-GaN-gated AlGaN/GaN high electron mobility transistors (HEMTs), with an emphasis on the key transistor-level parameters for digital and analog mixed-signal applications. In-situ measurements from room temperature (RT) to 500 °C show that trends in Vth, RON, ID,max and IG,max are largely as expected based on firstorder changes in the semiconductor properties. The fabricated transistors exhibited stable performance over 20 days at 500 °C. To the best of the authors’ knowledge, this work is the first systematic study on the HT performance of E-mode p-GaN-gated AlGaN/GaN HEMTs, and sheds light on their use in mixed-signal and low-voltage power circuits.

High Temperature Robustness of Enhancement-Mode p-GaN-Gated AlGaN/GaN HEMT Technology

In this work, the influence of various oxide electric field (۳ܠܗ (stress conditions on the gate oxide lifetime, gate leakage current, and threshold voltage of 1.2 kV 4H-SiC power planar metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. The results suggest that high ۳ܠܗ stress (> 9.4 MV/cm) applied to the gate oxide of commercial SiC power MOSFETs for a certain period degrades the oxide lifetime due to high Fowler-Nordheim (F-N) electron tunneling current followed by hole trapping. Moreover, hole trapping enhances the gate leakage current and reduces the threshold voltage. Therefore, the generation of holes under high electric field conditions should be avoided to ensure the reliability of SiC power MOSFETs.

Effects of Oxide Electric Field Stress on the Gate Oxide Reliability of Commercial SiC Power MOSFETs

瀆 It has been demonstrated that basal plane dislocations (BPDs)-induced stacking faults (SFs) cause body diode degradation in commercial 4H-SiC power MOSFETs, especially with higher voltage ratings. BPDs originate from 4HSiC boule, epi growth, and ion implantation. Considering the lower cost of ion implantation at room temperature (RT), this work investigates the potential of RT ion implantation replacing heated (HT) ion implantation by comparing the influence of both ion implantations on the body diode degradation of commercial 3.3 kV 4H-SiC power MOSFETs. We demonstrate with long-term (up to 1000 hours) forward current stress that RT implantation can keep the body diode degradation of 3.3 kV 4H-SiC power MOSFETs within the specification limits compared with HT implantation.

A Comparison of Ion Implantation at Room Temperature and Heated Ion Implantation on the Body Diode Degradation of Commercial 3.3 kV 4H-SiC Power MOSFETs

This paper presents a comparison of 1.2 kV 4H-SiC MOSFETs and Ti JBSFETs with deep P-well structures. For a fair comparison of the short-circuit characteristics between the MOSFETs and JBSFETs, an innovative design approach for the JBSFETs was implemented to obtain the same specific on-resistance to the MOSFETs. To improve the short-circuit characteristics of the MOSFETs and JBSFETs, channeling implantation was conducted to form a deep P-well structure, that helps reduce the maximum saturation current during the shortcircuit event. Using this approach superior short-circuit characteristics are achieved in the MOSFETs and JBSFETs. However, the JBSFETs provide a shorter shortcircuit withstand time than the MOSFETs due to the high leakage current from Schottky contact. Sentaurus 2D TCAD was used to understand and clarify the short-circuit mechanisms of the MOSFETs and JBSFETs. It was discovered that the MOSFETs failed due to the high current in the channel region, but the failure of JBSFETs happens in the Schottky contact. Moreover, solutions to improve the short-circuit characteristics of the JBSFETs are proposed; a narrow Schottky width and high work function metal.

A Comparison of Short-Circuit Failure Mechanisms of 1.2 kV 4H-SiC MOSFETs and JBSFETs

Neutron-induced failures in power electronics are a source of concern in many high-reliability applications. This paper describes how to estimate the device's decreased lifetime expectancy based on its usage. The physical mechanism, Failure in Time (FIT) statistics and FIT rate calculation methodology are presented. Several Microchip SiC MOSFETs and Schottky barrier diodes at different voltage ratings were tested, and the results for the excess FIT rate calculation based on various factors such as operation voltage, altitude, device area, latitude, and duty factor are presented.

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Design Optimization and Surge Current Capability of 4H-SiC Lateral Deep P+ JBS Diode on Thin RESURF Layer

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Design Optimization and Surge Current Capability of 4H-SiC Lateral Deep P+ JBS Diode on Thin RESURF Layer

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Comprehensive Modeling and Characterization of Photon Detection Efficiency and Jitter in Advanced SPAD Devices

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