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technical paper
Stabilizing skyrmions deterministically for racetrack memory applications
Magnetic skyrmions possess intriguing features such as ultra-small size, solitonic nature, and easy mobility with small electrical currents, which make them attractive for low power, high-density memory and logic applications (1). In a skyrmion-based racetrack, information can be encoded either by the presence and absence of skyrmions for Boolean computing or into the analog spatial coordinates of the skyrmions, which then can be translated into the timing information needed for temporal computing (2). However, it is essential to guarantee the positional stability of skyrmions for reliable information extraction because a randomly displaced skyrmion can alter the bit sequence and change the spatial coordinates thereby the encoded analog timings. Using micromagnetic simulations (3) for the minimum energy path (MEP), we compute the energy barriers associated with notches along a racetrack. We vary material parameters, specifically, the strength of the chiral Dzyaloshinskii-Moriya interactions (DMI), the notch geometry, and the thickness of the racetrack to get the optimal barrier height. We find a range of energy barriers up to ~ 45 kBT for a racetrack of 5 nm thickness that can provide a year-long positional lifetime of skyrmions for long-term memory applications while requiring a moderate amount of current (~ 1010 A/m2) to move the skyrmions (4). Moreover, we derive quasi-analytical equations to estimate the energy barrier with material-dependent pre-factor constants. Currently, we are building machine learning-based surrogate models for the computationally-expensive micromagnetics simulations to accelerate the energy barrier prediction for a much broader parameter space. Our results open up possibilities to design practical skyrmion-based racetrack geometries for spintronics applications.
References:
(1) H. Vakili, J. Xu and W. Zhou, J. Appl. Phys., 130, 070908 (2021)
(2) H. Vakili, and M. Sakib and S. Ganguly, IEEE J. Explor. Solid-State Comput. Devices Circuits, 1 (2020)
(3) A. Vansteenkiste, J. Leliaert and M. Dvornik, AIP Adv., 4, 107133 (2014)
(4) M. Morshed, H. Vakili and A. Ghosh, Phys. Rev. Appl., 17, 064019 (2022)