Implementation of spin transfer torque magneto-resistive random access memory (STT-MRAM) in memory chips requires that the write margin of the MRAM cell △Vwr, defined as the difference between breakdown voltage Vbd and write voltage Vwr for the specified endurance, write error rate and write speed, is sufficiently large in order to accommodate resistance variations arising from external chip circuitry (transistors, metal lines etc). Optimization of MRAM cell design and process as well as MRAM materials development aims at accomplishing these by either reducing Vwr, enhancing Vbd, or both 1. In this talk we will show that △Vwr can be increased by optimizing the MgO cap layer that is already present in a perpendicular MRAM cell, whose original intended function has been to increase perpendicular magnetic anisotropy energy of the free storage layer (FL) by adding additional Fe/MgO interface, and thus improve the MRAM retention 2. By increasing the thickness of the MgO cap layer to make its resistance-area product RA close to that of the main MgO barrier, we show that △Vwr can be increased substantially for the given write speed and endurance, without affecting thermal stability of the cell in a significant way. For example, for MRAM cells with diameters 50 - 60 nm we show that Vwr at 50% switching probability for 50 ns pulse width increases by about 0.28 V for thick cap (see Fig. 1(a)) while Vbd obtained by endurance measurements under bipolar stress at the same pulse width increases by almost 0.5 V, resulting in △Vwr improvement of approximately 0.2 V. We will discuss physical mechanisms underlying this finding and its technological importance.

References 1 D. Apalkov et al., Proc. of IEEE 104, 1796 (2016). 2 G. Jan et al., APEX 5, 093008 (2012).