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MMM 2022

November 07, 2022

Minneapolis, United States

Novel multi bit parallel pipeline

Spin transfer torque magnetoresistive RAM (STT-MRAM) is one of the promising emerging memory technologies, with the merits of CMOS-compatibility, fast read speed, high density and non-volatile, etc. (1). However, the write speed is one of the major challenges for STT-MRAM, especially in high speed applications. For a reliable writing operation, high writing current and enough duration time are required, which could decrease the life-time of the tunnel layer in the MTJ device and cause extensive power consumption. So, the writing strategy of the STT-MRAM is one of the key issues in the memory design. Several writing strategies are proposed to improve the writing reliability, lower the power consumption, as well as increase the life-time of the device. In the paper, the pipeline structure combined with the parallel shift register circuit is proposed to achieve the high write efficiency for the STT-MRAM. Figure 1 shows the block diagram of the proposed multi-bit parallel pipeline-circuit. In the designed circuit, the introduction of bit-parallel processing is essential to achieve high throughput operation (2).The parallel shift register circuit is added in the STT-MRAM to allow serial data to be transferred to the sensing circuit in parallel. Moreover, the pipeline structure is also utilized in the peripheral circuit. Several latches operating in response to a clock signal to process the data by dividing the write operation into a plurality of stages (3). Thus, the multi-bit parallel data can be carried out in pipelining manner, greatly increasing the average write speed and the throughput of STT-MRAM. The proposed write strategy of STT-MRAM achieves better write efficiency and high throughput, which has potential high speed application of STT-MRAM in the future. Fig.1 The block diagram of the proposed multi-bit parallel pipeline-circuit design for STT-MRAM.

(1) K. Huang, R. Zhao, N. Ning, et al., IEEE Trans. Circuits Syst., vol. 61, p. 2614-2623 (2014).
(2) R. Kashima, I. Nagaoka, M. Tanaka, et al. IEEE Trans. Appl. Supercond., vol.99, p. 1-1 (2021).
(3) Y. Ma, S. Miura, H. Honjo, et al., Jpn. J. Appl. Phys., vol. 59, p. SG (2020).

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