Spintronics-based devices offer certain key advantages like ease of fabrication with Si-substrate, non-volatile memory, low operational voltage, and non-linear device characteristics. Hardware security is a research domain that heavily relies on CMOS-based ICs, and the defense and attack mechanism is developed accordingly.
In this work, we explore shape anisotropy-based PMA Double barrier MTJ based on Verilog-A behavioral model (1) to design a possible Logic locking (2) system for Hardware Security. Logic Locking is a widely used security mechanism to counter multiple threats (3). Due to larger free layer thickness, the s-PMA DMTJ has better thermal stability even in the sub-10nm dimension. The current work focuses on Logic locking applications using this device, analyze its behavior under process variation in certain key parameters using Monte-Carlo simulations, and finally performs Eye-diagram performance analyses to test the design for high-speed digital logic applications. The results indicate that the s-PMA DMTJ has good thermal stability, smaller size (10nm dimension), robustness to device imperfections, and ability to work in high-speed digital circuits compared to other emerging MTJ structures such as STT MTJ, SOT MTJ, VG-SOT MTJ, etc.
Fig. 1(a) represents the block diagram of the logic Locking block, and Fig. 1(b) represents the circuit for implementing the desired operation. We have performed electrical simulations in TSMC 40nm CMOS generic process design kit using the cadence specter simulator with W/L ratio = 3, the temperature at 300K. Fig. 2(a) and 2(c) represent some circuit performance comparisons like the Eye-diagram test for high-speed circuits, and Table 1 presents the simulation data for the same. Fig. 2(b) shows that VG-SOT MTJ (4) fails the eye-diagram test for similar applications for comparison with s-PMA DMTJ.
(1) H. Wang et al., “Modeling and Evaluation of Sub-10-nm Shape Perpendicular Magnetic Anisotropy Magnetic Tunnel Junctions,” IEEE Transactions on Electron Devices, vol. 65, no. 12, pp. 5537-5544, Dec. 2018.
(2) H. M. Kamali, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “Advances in Logic Locking: Past, Present, and Prospects,” Cryptology ePrint Archive, 2022.
(3) S. Bhunia, and M. Tehranipoor, “Hardware security: a hands-on learning approach,” 1st Edition, 2018.
(4) K. Zhang, D. Zhang, C. Wang, L. Zeng, Y. Wang and W. Zhao, “Compact Modeling and Analysis of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction,” IEEE Access, vol. 8, pp. 50792-50800, 2020.
(5) K. Watanabe et al., “Shape anisotropy revisited in single-digit nanometer magnetic tunnel junctions,” Nature Communication, 2018.