With the rapid growth of technologies such as the Internet of Things (IoT) and artificial intelligence (AI) in recent years, giant data transmission and processing capacities of computers have faced major hurdles (1, 2). At the moment, memory is the key bottleneck in computer processing big data processes. The CPU and the memory are distinct in the standard Von Neumann design, while frequent data exchange uses a lot of energy, resulting in the "Memory Wall" problem (3). On-chip cache, being the crucial constituent of CPU, accounts for a pivoltal portion of the system's overall power consumption. If the power wastage of the on-chip cache could be lowered, the ultimate performance of the CPU can be strengthened. The typical SRAM-based cache is vulnerable to high static leakage power consumption, and scaling up its capacity is challenging. Magnetic random access memory (MRAM) (4), as a new non-volatile storage technology, is expected to break the limitation at the cache level (5). In the paper, MRAM cache is used to limit static leakage power consumption. A quad-core CPU MRAM hierarchical cache system is established in the designed MRAM cache, with the high-speed Spin-Orbit-Torque (SOT)-MRAM (6) functioning as the L1 cache and the high-density Spin-Transfer-Torque(STT)-MRAM (7) serving as the L2 shared cache. A non-inclusive allocation method is adopted for the data-exchange strategy, by which the number of the write operation in the L2 STT-MRAM cache is reduced, and the energy consumption of the system is further reduced. The designed system is simulated and verified based on gem5 (8) software framework. The simulation results show that strategy of the hybrid MRAM memory is a promising candidate for high-speed and low-power on-chip cache.

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