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Monolayer 2D material WSe2 provides an unique platform for exploring the generation and control of spin and valley polarization. In this work we conduct Kerr rotation measurements on monolayer WSe2 transisors to show the electrical control and temperature dependence of the spin and valley polarization generated by the spin and valley Hall effect (SVHE). A drift-diffusion theory along with the reflection spectra and electrcal IV curves are used to interpret the data and extract meaningful parameters.

DRC 2022

Controlling the Spin and Valley Hall Effect in Monolayer WSe2 at Elevated Temperatures

kerr rotation

monolayer wse2

spin and valley hall effect

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### ** History of DRC**
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In the ensuing decades, many exciting firsts were presented at SSDRC, including the use of impurity diffusion in silicon and germanium, the first practical MOSFET, and the first lattice-matched heterojunction.

In 1969, under the leadership or Herbert Kroemer and Cal Quate, the CEDR and SSDRC merged into DRC. In 1970, attendance was opened to all, and the first DRAM (dynamic random-access memory), room temperature lasers, and first CCD (charge-coupled device) were reported—all in the same 1970 DRC meeting!

1976 saw the first official coordination of tandem meetings between DRC and the Electronic Materials Conference (EMC) to bring together the electronic materials and device communities—a custom which persists to this day. In 1991, DRC began publishing its digest with IEEE; they can all be found [here on IEEE Xplore](https://ieeexplore.ieee.org/xpl/conhome/1000199/all-proceedings). Throughout this period, DRC featured reports of many novel and record-setting devices, including the HEMT (High Electron Mobility Transistor), VCSEL (Vertical Cavity Surface Emitting Laser), HBT (Heterojunction Bipolar Transistor), and nanoscale MOSFETs.

In recent years, DRC has continued to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an [article in the Journal of the Electron Device Society](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486). DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Today, as we look forward to the next 75+ years of device innovation, DRC continues to lead the way in showcasing top-caliber research, facilitating vibrant discussion and debate and acting as a platform to nurture the next generation of device engineers. We welcome you to join us at the next DRC!

To learn more about DRC's history, please see [Aaron Franklin, Debdeep Jena and Deji Akinwande, "75 Years of the Device Research Conference—A History Worth Repeating," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 116-120, 2018. doi: 10.1109/JEDS.2017.2780778](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486).

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Registration Is Required

DRC continues to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an article in the Journal of the Electron Device Society. 
DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

A new approach of pulsed current-voltage (I-V) protocol has been applied that reveals current settling. This protocol minimizes metal-FE interface charging and directly reveals amplitude-dependent polarization continuation. Measurement of electroresistance ratio shows it is possible to detect opposite-state or same-state polarization, but not without partial polarization change.

Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory Implications for Partial State Storage

Two-dimensional (2D) materials and their heterostructures are promising for memristive applications due to their extreme scalability and high performance.1 Threshold switching in 2D-Transition Metal Dichalcogenide (TMDC) memristors has been previously identified for neuromorphic applications.2 On the other hand, accurate control of defect concentration in 2D-TMDC films is necessary for optimized performance of the memristive devices. In this work, we explore a chemical route to control defect concentration in 2D-MoS2 films. We demonstrate that the defect concentration in 2D-MoS2 can be tuned by H2O2 treatment. We then optimize the resistance switching behavior of Au/MoS2/Ag/Au memristors to obtain reliable threshold resistance switching with high on/off ratio, low operating voltages and self-compliance behavior. This work offers promise for a low-cost, scalable approach to develop 2D-TMDC based high-performance neuromorphic hardware.

Controllable Defect Engineering in 2D-MoS2 for high-performance threshold switching memristive devices

In this research, we investigated the effect of low sputtering power for 5 nm thick ferroelectric nondoped HfO2 gate insulator formation to improve the operation speed and operation voltage of scaled MFSFET. Sputtering power of 50 W for 5 nm thick ferroelectric nondoped HfO2 gate insulator formation was effective not only to increase the memory window but also to reduce the low frequency noise spectral density of MFSFET with the improvement of interface property.

Ultrathin Ferroelectric Nondoped HfO2 for MFSFET with High-speed and Low-voltage Operation

Late News: High Voltage β-Ga2O3 Lateral Schottky barrier diode with High Permittivity Dielectric RESURF demonstrating > 1 GW/cm2 Power Figure of Merit

Here, we demonstrate improvement in the mobility and on-state current of monolayer MoS2 transistors using a high-tensile-stress SiNx capping layer. We demonstrate its applicability to achieve high currents in both back- and top-gated device configurations. We achieve up to 47% improvement in back-gated FET mobility and on-state current, then extend the technique to achieve 33% improved current drive in top-gated FETs, with record saturation current up to 488 μA/μm in a 200 nm long channel.

Mobility Enhancement of Monolayer MoS2 Transistors using Tensile-Stressed Silicon Nitride Capping Layers

We investigate the impact of oxide traps on the performance of 300 mm integrated dual-gate WS2 FETs. First, we develop a simple analytical model to describe the electrostatics of our FET design and compare it with TCAD simulations. Afterwards, we perform BTI measurements using several combinations of gate stress and gate sweep to determine the density of active traps based on our electrostatics understanding.

Analysis of BTI in 300 mm integrated dual-gate WS2 FETs

In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon field-effect transistors (FETs) in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/μm (near 20 mA/μm) is achieved in an In2O3 GAA nanoribbon FET with a channel thickness (T¬IO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm. The record high drain current is about one order of magnitude higher than any conventional single-channel semiconductor FETs.

Late News: A Gate-All-Around Single-Channel In2O3 Nanoribbon FET with Near 20 mA/µm Drain Current

The SiGeSn semiconductors have opened a new route for the development of all-group-IV-based optoelectronic devices. This talk will present the recent progress for the development of SiGeSn technology, including the material growth using commercial chemical vapor deposition reactor, demonstration of optically pumped and electrically injected lasers, light emitting diodes (LEDs) and photodetectors.

SiGeSn Technology for All-Group-IV Photonics

This presentation will give an overview of the current status and future opportunities for high-frequency ultrawide bandgap (UWBG) semiconductor transistors. GaN-based transistors have demonstrated excellent performance for RF applications, , but are close to the limits set by their electronic properties in the mm-wave regime. UWBG semiconductors such as high Al-content AlGaN can provide significantly higher breakdown electric field while having electron saturated velocity similar to GaN, and can in principle provide significant improvements in power-gain product at mm-wave frequencies. However, key challenges in real devices such as high contact resistance, premature breakdown of metal-semiconductor and dielectric interfaces, and thermal management must be addressed before such improved performance is realized.

Ultra-Wide Bandgap Semiconductor Transistors for mm-wave Applications

In this work, we introduce N-polar HEMTs on single crystal aluminum nitride (AlN) substrates with a GaN/AlGaN/AlN heterostructure. The homoepitaxially grown AlN layer and the N-polar structure offer many advantages over the conventional Ga-polar AlGaN/GaN HEMTs, such as high breakdown voltage, superior thermal management, stronger electron confinement, and low-resistivity ohmic contact. The first DC results of the device will be presented, and these results will help guide us in creating high performance RF HEMTs with minimal thermal issues.

Controlling the Spin and Valley Hall Effect in Monolayer WSe2 at Elevated Temperatures

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Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory Implications for Partial State Storage

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Controlling the Spin and Valley Hall Effect in Monolayer WSe2 at Elevated Temperatures

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Next from DRC 2022

Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory Implications for Partial State Storage

Similar lecture

Mechanism study of sodium storage in phthalocyanine based electrode materials

Stay up to date with the latest Underline news!

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