United States

A versatile but extremely compact memristor model is introduced that is capable of emulating various memristive technologies while featuring fully analog, flux-linkage controlled operation as well as temporal tunability. Computation with time is a layer of complexity that could help break through barriers in the field of non-traditional compute and is extremely bio-mimetic, as the brain is exceptionally adept at temporal processing. This talk will explore some examples of temporal computation using simulated memristive hardware.

DRC 2022

An Experimentally Validated, Universal Memristor Model Enabling Temporal Neuromorphic Computation

biomimetic

temporal

brain

memristors

computation

neuromorphic

model

Naval Information Warfare Center Pacific is partnering with AFCEA San Diego chapter to host the workshop.

The NAML workshop is an opportunity for researchers from Navy research and development centers and our partner organizations to exchange technical ideas and to come together as a team.

The goals of NAML are:

* To spread awareness of current machine learning research relevant to Naval applications

* To connect machine learning researchers with experts in military requirements

* To build and strengthen collaborations within the defense research community

**Watch this video to hear about the AFCEA purpose.**

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NAML 2021

technical paper

[![](https://assets.underline.io/uploads/markdown_image/1/image/985c8a40b04e56675221c8549975de3c.png)](https://drive.google.com/file/d/1B70nPIeeeqdG4UU70NlYXuKVOHLRuJEo/view?usp=sharing)

### ** History of DRC**
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In the ensuing decades, many exciting firsts were presented at SSDRC, including the use of impurity diffusion in silicon and germanium, the first practical MOSFET, and the first lattice-matched heterojunction.

In 1969, under the leadership or Herbert Kroemer and Cal Quate, the CEDR and SSDRC merged into DRC. In 1970, attendance was opened to all, and the first DRAM (dynamic random-access memory), room temperature lasers, and first CCD (charge-coupled device) were reported—all in the same 1970 DRC meeting!

1976 saw the first official coordination of tandem meetings between DRC and the Electronic Materials Conference (EMC) to bring together the electronic materials and device communities—a custom which persists to this day. In 1991, DRC began publishing its digest with IEEE; they can all be found [here on IEEE Xplore](https://ieeexplore.ieee.org/xpl/conhome/1000199/all-proceedings). Throughout this period, DRC featured reports of many novel and record-setting devices, including the HEMT (High Electron Mobility Transistor), VCSEL (Vertical Cavity Surface Emitting Laser), HBT (Heterojunction Bipolar Transistor), and nanoscale MOSFETs.

In recent years, DRC has continued to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an [article in the Journal of the Electron Device Society](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486). DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Today, as we look forward to the next 75+ years of device innovation, DRC continues to lead the way in showcasing top-caliber research, facilitating vibrant discussion and debate and acting as a platform to nurture the next generation of device engineers. We welcome you to join us at the next DRC!

To learn more about DRC's history, please see [Aaron Franklin, Debdeep Jena and Deji Akinwande, "75 Years of the Device Research Conference—A History Worth Repeating," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 116-120, 2018. doi: 10.1109/JEDS.2017.2780778](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486).

### **Topics**
* Biological Devices
* Devices for Extreme Conditions
* Heterogeneously Integrated Devices
* Memory Devices
* Modeling and Simulation of Devices
* Nanoscale and Vacuum Devices
* Optoelectronic and Optical Devices
* Other Emerging Devices
* Power Devices
* Quantum Devices
* RF and Terahertz Devices
* Spintronic and Magnetic Devices
* Thin-film Devices
* Wide-bandgap Devices
 
### **Invited Speakers**
* Patrick Fay, University of Notre Dame
* Susanne Hoffmann-Eifert, Peter Grünberg Institute
* Sanghyeon Kim, Korea Advanced Institute of Science and Technology
* Sriram Krishnamoorthy, University of California, Santa Barbara
* Mario Lanza, King Abdullah University of Science and Technology
* Xiuling Li, The University of Texas at Austin
* Marko Radosavljevic, Intel Corporation
* Siddharth Rajan, The Ohio State University
* Giordano Scappucci, Delft University of Technology
* Fisher Yu, University of Arkansas
* Wenjuan Zhu, University of Illinois at Urbana-Champaign




Registration is required to attend this event. If you have not already done so, please use the link below to register for a ticket to the conference:

https://www.mrs.org/drc-2022/registration

Registration Is Required

History of DRC
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In this work, we demonstrate vertically stacked multilayer atomic-layer-deposited sub-1nm In2O3 field-effect transistors (FETs) with surrounding gate in a back-end-of-line (BEOL) compatible low-temperature fabrication process. Multilayer FETs with number of In2O3 layers up to 4 and 1.2 nm-thick HfO2 between each individual layer are fabricated. An enhancement of on-state current (ION) from 183 μA in single layer In2O3 FET to 339 μA in 4 layer device with on/off ratio of 3.4×10^4 is achieved.

Vertically Stacked Multilayer Atomic-Layer-Deposited Sub-1-Nanometer In2O3 Field-Effect Transistors with BEOL Compatibility

For p-type Cu2O thin film transistors (TFTs), high contact resistance is one of the critical issues that limit field effect mobility. Thus, to alleviate the contact resistance issue, in this work, we for the first time demonstrated Cu2O TFTs with nitrogen-doped Cu2O S/D interlayer. We observe a reduced contact resistance and improved field effect mobility when the N:Cu2O S/D interlayer is used.

N:Cu2O S/D for low contact resistance p-type Cu2O thin film transistor

Metal oxides (e.g., In2O3, InZnO) have been demonstrated to be excellent materials for flexible electronics. Solution-processed methods offer a cost-effective and high uniformity route to deposit the metal oxides on a variety of substrates. However, post-processing is often necessary and it becomes a challenge on plastic substrates. Here, we explore photonic curing to process the semiconductor material without substantially heating the plastic substrate.

Photonic Curing: Rapid Thermal Processing of Oxide Thin-film Transistors on Plastic

In this work, atomically thin ALD Zn-doped or InZnO are investigated for the first time as a BEOL channel. Outstanding device performance on InZnO transistors is achieved including on-off current ratio of 1e7 and 1e9, on-current density of 1.6 A/mm and 1.2 A/mm with In:Zn ALD cycle ratio of 10:1 and 5:1, respectively, without optimization annealing. This work provides a new route to explore new BEOL oxide semiconductor channels beyond In2O3 achieving better current saturation at higher drain voltage and higher power amplification

Atomically-thin atomic-layer-deposited InZnO transistors with BEOL compatibility

Monolayer 2D material WSe2 provides an unique platform for exploring the generation and control of spin and valley polarization. In this work we conduct Kerr rotation measurements on monolayer WSe2 transisors to show the electrical control and temperature dependence of the spin and valley polarization generated by the spin and valley Hall effect (SVHE). A drift-diffusion theory along with the reflection spectra and electrcal IV curves are used to interpret the data and extract meaningful parameters.

Controlling the Spin and Valley Hall Effect in Monolayer WSe2 at Elevated Temperatures

Late News: High Voltage β-Ga2O3 Lateral Schottky barrier diode with High Permittivity Dielectric RESURF demonstrating > 1 GW/cm2 Power Figure of Merit

Here, we demonstrate improvement in the mobility and on-state current of monolayer MoS2 transistors using a high-tensile-stress SiNx capping layer. We demonstrate its applicability to achieve high currents in both back- and top-gated device configurations. We achieve up to 47% improvement in back-gated FET mobility and on-state current, then extend the technique to achieve 33% improved current drive in top-gated FETs, with record saturation current up to 488 μA/μm in a 200 nm long channel.

Mobility Enhancement of Monolayer MoS2 Transistors using Tensile-Stressed Silicon Nitride Capping Layers

We investigate the impact of oxide traps on the performance of 300 mm integrated dual-gate WS2 FETs. First, we develop a simple analytical model to describe the electrostatics of our FET design and compare it with TCAD simulations. Afterwards, we perform BTI measurements using several combinations of gate stress and gate sweep to determine the density of active traps based on our electrostatics understanding.

Analysis of BTI in 300 mm integrated dual-gate WS2 FETs

In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon field-effect transistors (FETs) in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/μm (near 20 mA/μm) is achieved in an In2O3 GAA nanoribbon FET with a channel thickness (T¬IO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm. The record high drain current is about one order of magnitude higher than any conventional single-channel semiconductor FETs.

Late News: A Gate-All-Around Single-Channel In2O3 Nanoribbon FET with Near 20 mA/µm Drain Current

The SiGeSn semiconductors have opened a new route for the development of all-group-IV-based optoelectronic devices. This talk will present the recent progress for the development of SiGeSn technology, including the material growth using commercial chemical vapor deposition reactor, demonstration of optically pumped and electrically injected lasers, light emitting diodes (LEDs) and photodetectors.

An Experimentally Validated, Universal Memristor Model Enabling Temporal Neuromorphic Computation

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Vertically Stacked Multilayer Atomic-Layer-Deposited Sub-1-Nanometer In2O3 Field-Effect Transistors with BEOL Compatibility

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An Experimentally Validated, Universal Memristor Model Enabling Temporal Neuromorphic Computation

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Next from DRC 2022

Vertically Stacked Multilayer Atomic-Layer-Deposited Sub-1-Nanometer In2O3 Field-Effect Transistors with BEOL Compatibility

Similar lecture

Brain Inspired Quantum and Neuromorphic Machine Learning

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads